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  • SystemC Interoperability - Are We There Yet?

    The biggest challenge in system-level design is modeling, and getting SystemC models to work together in simulation environments has been a long, hard struggle. Finally, it appears that the stars are aligned and we are converging on the three things we need for SystemC model interoperability –...
    Posted to Industry Insights (Weblog) by rgoering on Tue, May 19 2009
  • OSCI Launches Video Tutorials for TLM 2.0

    Cadence is one of the sponsors of a series of Open SystemC Initiative (OSCI) TLM 2.0 tutorials, first delivered at DVCon 2009. They have been captured in video form for your access, anytime, anywhere! The Tutorials Agenda: Introduction and Welcome Jack Donovan, President, XtremeEDA USA Overview of TLM...
    Posted to System Design and Verification (Weblog) by Steve Brown on Tue, May 5 2009
  • Predictions for 2009

    Having summarized the main verification technology-specific observations that the "Trailblazer" team saw in 2008 , which to recap were: 1 - 1 billion logic gate chip roadmaps are here 2 - True "Metric Driven Verification" (MDV) starts to evolve from CDV 3 - The "language war"...
    Posted to Functional Verification (Weblog) by jvh3 on Tue, Jan 13 2009
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