Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
More Products
OrCAD Products
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
IP Alliances
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Quicklinks
All Blogs
All Forums
Community Search
CDN
Live!
User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> OSCI
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Manufacturability Signoff
All Blog Categories
Popular Tags
Allegro
ARM
Custom IC Design
DAC
Digital Implementation
e
EDA360
encounter
ESL
Functional Verification
Incisive
industry insights
Logic Design
Low power
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
SystemVerilog
TLM
UVM
verification
Virtuoso
Browse All Tags
Share
Email
Social Web
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
OSCI
2010
2011
2011 standards
3D-IC
ABV
Acceleration
Accellera
Accellera and OSCI
Accellera Systems Initiative
Accellera-OSCI
AMS
analysis
AOP
architect
ARM
ARM Techcon
bare metal software
Brophy
Cadence
Calypto
CCI
Cortex-A9
Cortex-M3
CPF
DAC
DFM Coalition
drivers
DVCon
DVCon 2012
e
e language
EDA
EDA standards
EDA360
embedded software
Eric Lish
ESL
fast models
formal
formal verification
Functional Verification
Gary Smith
George Frazier
Goodenough
high level synthesis
High-level Synthesis
hls
Hogan
horses
HW/SW
IEC
IEEE
IEEE 1647
IEEE 1666
IEEE 1734
IEEE 1800
IEEE 1801
IEEE P1666
Incisive
Industry Insights
interoperability
IP
IP quality
IP-XACT
Jim Hogan
Krolikoski
Lish
low power
Mixed-Signal
NASCUG
OpenAccess
OpenPDK
OVM
process control
Rawat
RTL
SCE-MI
Si2
SoC Realization
Spirit
standards
System C
System Design and Verification
System Design and Verification
system realization
SystemC
SystemC-AMS
SystemVerilog
TLM
TLM 2.0
TLM-2
TLM-2.0
town hall
UCIS
UPF
UVM
UVM 1.0
verification
virtual platforms
virtual prototypes
DVCon 2012: Accellera “Town Hall” Meeting Explores Future of EDA Standards
How will EDA standards move forward, now that the Accellera standards organization and the Open SystemC Initiative (OSCI) have merged into the Accellera Systems Initiative ? That was the topic of a "town hall" forum lunch at the DVCon conference Feb. 27, 2012. No presentations here, no speeches...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Feb 27 2012
2011 EDA Standards Update and 2012 Forecast
As system complexity grows and semiconductor process nodes shrink, EDA industry standards are more important than ever. With today's time-to-market pressures, the last thing you'd want to do is waste time due to incompatible formats, tools or methodologies. Fortunately, 2011 was a productive...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Dec 21 2011
Equine Anatomy, Pax Romana and the Reach of Standards
At the recent Synopsys EDA Interoperability Forum, the opening session focused on a 10 year review of standards and interoperability between EDA tools. Three speakers -- Philippe Magarshack (Central R&D Group VP, STMicroelectronics), John Goodenough (Vice-President of Design Technology and Automation...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Wed, Dec 14 2011
Accellera-OSCI Union Completed – What It Means for EDA Standards
Two prominent EDA industry standards organizations -- Accellera and the Open SystemC Initiative ( OSCI ) - announced today (Dec. 5) the completion of their merger under the name "Accellera Systems Initiative." The stage is now set for a unified EDA standards effort that cuts across multiple...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Dec 5 2011
ARM TechCon Paper: Using a Virtual Platform for Multi-Core Software Development
You may have heard that "virtual platforms" enable software development and debugging before system hardware is available. But how do you build them, how do you solve common problems, and how do you debug software and hardware for multi-core systems? These questions and more were answered in...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Nov 21 2011
IEEE Revises SystemC for 2011 – What’s In It For Users
More than any other language standard, SystemC has made system-level design possible. It is the lifeblood of high-level synthesis, virtual prototyping, and transaction-level verification. Thus, the first IEEE revision of the standard in six years -- announced today (Nov. 10, 2011) as IEEE 1666-2011 ...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Nov 10 2011
Accellera – OSCI Union: New Synergy for EDA Standards?
Two leading EDA industry standards organizations - Accellera and the Open SystemC Initiative ( OSCI ) - announced their intent to merge into a "new organization" today (June 22, 2011). The move will bring most "front end" EDA standards (RTL and above) under one roof, and potentially...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jun 22 2011
How EDA360 “Realizations” Leverage Industry Standards
The EDA360 vision , articulated by Cadence one year ago, is not about one company - it's a vision for an entire industry. As such, EDA360 depends on a collaborative ecosystem with many players, including other EDA vendors, silicon IP providers, foundries, design services companies, and many others...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, May 9 2011
Video: SystemC Update From OSCI Chair Eric Lish
Eric Lish, manager of virtual platforms at Intel's Technology and Manufacturing Group, has been chair of the Open SystemC Initiative ( OSCI ) since October 2009. At the North American SystemC User Group ( NASCUG ) meeting at the DVCon conference Feb. 28, I had the opportunity to do a brief video...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 9 2011
UVM Meets SystemC and VHDL in DVCon “Town Hall” Forum
Should the Universal Verification Methodology (UVM) work with SystemC? Should VHDL be extended with the object-oriented capabilities of SystemVerilog? Is it better to have interoperability between languages, or a unified language, or a language-neutral verification methodology? These questions and more...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Mar 1 2011
Page 1 of 3 (30 items) 1
2
3
Next >