Home > Community > Tags > OOP

	Login with a Cadence account.
Not a member yet? Create a permanent login account to make interactions with Cadence more conveniennt. Register \| Membership benefits

Get email delivery of the Cadence blog (individual posts).

Popular Tags

Browse All Tags

Email
Social Web

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Send yourself a copy

Cadence RSS Feeds

Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Send Yourself A Copy

OOP

Technical Tip on How to Use HDL Assertions in e

While assertion callbacks have existed in Specman/e for several years now, several questions on their usage have surfaced recently, so here is a short refresher on their usage. ABV (Assertion Based Verification) is, more and more, becoming an important aspect of any complete verification. HDL assertions...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Sep 28 2011
At DVCon 2011 Next Week

Next week my colleagues and I will be at DVCon 2011 in force, ready to regale you with technical papers, panels, and techtorials covering the full range of functional, assertion-based, mixed-signal, and transaction-level verification topics. If you are within a tank of gas or a Southwest flight of San...

Posted to Functional Verification (Weblog) by jvh3 on Fri, Feb 25 2011
e Templates: A Nifty Way To Create Reusable Code

Hi All, An e template (known as a parameterized type in other programming languages) is a feature that has been around for several releases and can be a great way of creating re-usable code. Templates can be used anywhere a user would like to create a single re-useable object that might operate on different...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Aug 10 2010
e Verification Job Postings We’ve Seen

Specmaniacs between jobs: over the last few weeks we’ve seen job postings for verification engineering in general, and e/Specman expertise in specific, in the LinkedIn groups: “Experts in SystemVerilog/Specman/VERA/System C” “Think Verification” “HVL (SystemC/C++/Verilog...

Posted to Functional Verification (Weblog) by teamspecman on Fri, Aug 6 2010
New UVM Book Is For You And U But Not Ewe

A Practical Guide to Adopting the Universal Verification Methodology (UVM) is the first book published on the emerging Accellera UVM . Written by the main authors of the user guide in the UVM release, this book provides more details and extends the methodology to address system level challenges. Unlike...

Posted to Functional Verification (Weblog) by Adam Sherilog on Wed, Jul 21 2010
When Less Is More, Part 3: Is e code really “infinitely” more compact than SystemVerilog?

Building on the packet generation example of part 1 , and the coverage examples of part 2 that compare the ratio of lines e code to lines of SystemVerilog for a given task, in this post I’m going to show you how to “divide by 0” and leverage e capabilities that simply don’t exist in SystemVerilog, technically...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Apr 21 2010
When Less Is More, Part 1: Is e Really Up to 3x More Compact Than SystemVerilog?

A famous expression in the software world is that “you can only expect 10 good lines of production code per day”. Web search for this phrase and you will see there is ongoing debate whether this figure is still only 10 lines, or it’s improved to 20, or 100, or more. One thing that’s...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Mar 30 2010
Challenging Misconceptions About Verification Languages

One thing I learned from the recent DVCon conference is that there are a number of common misconceptions about hardware verification languages (HVLs). I had a few of these myself. Two provocative and well-attended presentations provided a different way of looking at HVLs: "Apples Versus Apples HVL...

Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 10 2010
Why OOP Falls Short For Verification

Last week at DVCon , frequent Team Specman guest blogger Matan Vax of R&D gave a paper on "Where OOP Falls Short of Verification Needs". In the following video, Matan elaborates on his paper, where it becomes clear that OOP languages like -- well, you know -- are at an inherent disadvantage...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Mar 3 2010
DVCon 2010 - Day 3

Click here or on the image below to go to the annotated photo blog of DVCon 2010 Day 3. The images and notes include highlights from: A paper on "Where OOP Falls Short of Verification Needs" (And there is also a video interview of Matan elaborating on the paper The paper "Tweak Free Reuse...

Posted to Functional Verification (Weblog) by jvh3 on Tue, Mar 2 2010

Page 1 of 2 (16 items) 1 2 Next >

Popular Tags

Share

Subscribe

Contact Us

OOP

Technical Tip on How to Use HDL Assertions in e

At DVCon 2011 Next Week

e Templates: A Nifty Way To Create Reusable Code

e Verification Job Postings We’ve Seen

New UVM Book Is For You And U But Not Ewe

When Less Is More, Part 3: Is e code really “infinitely” more compact than SystemVerilog?

When Less Is More, Part 1: Is e Really Up to 3x More Compact Than SystemVerilog?

Challenging Misconceptions About Verification Languages

Why OOP Falls Short For Verification

DVCon 2010 - Day 3