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  • Generate OrCAD Netlist and BOM from Command Line

    I'm trying to generate a netlist and BOM from a given OrCAD DSN from the command line (for integration within my version control). For netlist generation I found (from searching the forums) pstswp.exe. Unfortunately I couldn't find any documentation on this, and it doesn't give any help information...
    Posted to PCB Design (Forum) by iWaldo on Tue, Aug 26 2014
  • Create Netlist removes some net members of a Net-Class

    Hi, I am working with Allegro PCB 16.6. I see a very strange phenomena in my design. When I try create netlist in Capture and load it to *.brd file I see that it has removed some net members of a defined net class?!. :-( I don't see why and how this can happen. Can anybody please help?! Thanks all...
    Posted to PCB Design (Forum) by Hossein1357 on Sat, Aug 23 2014
  • X over pad in PCB editor

    Hi Guys, I've only been using ORCAD for about 2 months now, so I'm sure this is a silly problem. I seem to have an issue with one of my nets - I am getting an "x" over all of the pads in the net and not a single component appears to get associate with that net. I have attached a screenshot...
    Posted to PCB Design (Forum) by zquinn3 on Tue, Jul 29 2014
  • OSS netlisting inherited gnd problem

    Dear all, we are having a strange issue when netlising our design with the OSS netlister (via runams command-line). Some of the inherited grounds nets are being strangely netliested. For instance, an inherited net that should be netlisted as \vss! ; is being netlisted as \vss_vss! ; that is, its name...
    Posted to Custom IC Design (Forum) by freitas on Thu, Jul 24 2014
  • How to not netlist a certain symbol

    Good day! I want to make library that when added to schematic, the instances are not netlisted during spectre simulation. The symbols does not have models and are designed for CDF parameter extraction only. I have a reference LIBRARY with this property but I can not find out how it was implemented. I...
    Posted to Custom IC SKILL (Forum) by alainmelan on Thu, Jul 3 2014
  • Parametric analysis - voltage error in the netlist

    I found that when I run parametric sweep with fine voltage step, netlists are sometimes generated with wrong value. For example, when I run parametric analysis with the voltage changing from 0 to 1V with 1/2560V(=390.625uV) step, 62.5mV is changed to 62.4999999999998V in the netlist. Is there some kind...
    Posted to Custom IC Design (Forum) by Seokhyun Jeong on Mon, Apr 28 2014
  • Need to trace a path from a port to all the memory_instance it is connected

    HI All, Have a query on First Encounter tool. I have a port(abc) which is connected to all the memory_pin(abc) in the design through aob's I need to trace the connectivity and dump_out the complete path through that port Second is there a way to hightlight in layout like how they are placed or view...
    Posted to Digital Implementation (Forum) by Anuragjn on Mon, Feb 3 2014
  • Modify netlist of a block and resimulate (CDL.... CDF....)

    Hello everyone, I am trying to pinpoint a layout error mechanism by modifying the av_extracred view netlist and resimulating the testbench. I have managed to create a manually written netlist as a spectre view before by following this tutorial: http://www.cadence.com/Community/blogs/rf/archive/2009/01...
    Posted to Custom IC Design (Forum) by cozdag on Sat, Dec 28 2013
  • Netlist failure - duplicate Name issue

    I have a multi-page design originally created in Capture 10. Now that I'm making a netlist in Capture 16.5, I got an mismatch error between xprt and xnet. After a quick search, it's quite clear that the problem is a shared Name field by two instances on different pages. According to http://www...
    Posted to PCB Design (Forum) by B Price on Tue, Nov 19 2013
  • Force ams netlister to skip ports/pins

    Hello, Andrew! I want to skip several ports of the symbol during schematic netlisting for ams simulation. How can I do it? (As far as know there is a kind of property to be added to the pin) Netlister revision: // AMS netlist generated by the OSS based AMS netlister // IC subversion: IC6.1.5-64b.500...
    Posted to Custom IC Design (Forum) by Runner on Sat, Aug 24 2013
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