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NanoRoute

10nm and 14nm FinFETs Pose Challenges – But Collaboration Brings Solutions

10nm and 14nm FinFET design will have a lot of challenges, but collaboration among semiconductor ecosystem partners is finding solutions, according to a presentation given at the Common Platform Technology Forum Feb. 5, 2013. The presentation was given by Vassilios Gerousis (right), distinguished engineer...

Posted to Industry Insights (Weblog) by rgoering on Tue, Feb 12 2013
NanoRoute doesn't route multi height design

Hello, as a test case I have a mixed design with 4 rows only. 3 standard core cell rows and 1 second row, that has a multiple of standard cell row height & pitch. Site definition is done properly. The design contains 2 cells only, one per each row. I created the floorplan, defined the globalNetConnect...

Posted to Digital Implementation (Forum) by scudex on Wed, Feb 6 2013
Five-Minute Tutorial: Why You Should Be Running Early DRC

Everyone knows you have to run signoff DRC before you tape out a design. Sometimes, DRC is left to exactly that moment - right before the tapeout. If major problems are found in the design at that point, the tapeout either has to be delayed, or there is a mad scramble to fix the issues. This is a situation...

Posted to Digital Implementation (Weblog) by Kari on Thu, Oct 11 2012
Simple Steps to Debug DRC Violations Undetected in EDI System

You've placed and routed your design in the Encounter Digital Implementation (EDI) System. It passed Verify Geometry and Verify Connectivity without a violation. Great! But when you run DRC signoff with your physical verification tool, you have violations related to the routing. What should you do...

Posted to Digital Implementation (Weblog) by wally1 on Mon, Sep 10 2012
10 Encounter Tips and Tricks You May Not Be Aware Of

In looking over the shoulders of Encounter users over the years I've found there's a bunch of little tips and tricks I use to make interacting with the tool a little easier that aren't necessarily immediately obvious. Here are some of the more common ones I used this week: When navigating...

Posted to Digital Implementation (Weblog) by BobD on Fri, Jul 27 2012
Improve Your Productivity With Rapid Adoption Kits (RAKs) for Encounter Digital Implementation (EDI) System and Sign-off Flow

As you know, Cadence Online Support is your 24/7 site for getting help and resolving issues related to Cadence software. If you are signed up for e-mail notifications, you've noticed new solutions, application notes, videos and other content are added daily. In this blog I want to highlight a new...

Posted to Digital Implementation (Weblog) by wally1 on Mon, Jul 9 2012
When One Via Just Doesn’t Cut It – Recommended Settings for NanoRoute Including Multi-cut Via Insertion Flows

Maximizing the usage of Multi-cut vias by the router is one key to improving yield. And at advanced nodes it is essential step in the flow. So what are the proper settings and flow to use to maximize multi-cut via insertion with NanoRoute? And how do I know if I'm using the latest recommended settings...

Posted to Digital Implementation (Weblog) by wally1 on Thu, Apr 5 2012
ARM TechCon Paper: Inside Story of a 20nm Test Chip Tapeout

In March 2011, ARM, Cadence and Samsung launched a collaborative effort to design a 20nm test chip based on nanoSTEP (nSTEP), a microcontroller reference platform based on the ARM Cortex-M0 processor. This chip taped out just two months later and was formally announced in July . At the recent ARM TechCon...

Posted to Industry Insights (Weblog) by rgoering on Thu, Dec 8 2011
“In Design” DFM Signoff – the Inside Story

As noted in a recent customer announcement with Fujitsu, Cadence offers "in design" design for manufacturability (DFM) signoff for digital, mixed-signal and custom IC design. The basic idea is simple - engineers run signoff DFM checks during the physical design process, instead of waiting until...

Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 5 2011
Five-Minute Tutorial: Fixing SI Victim Nets

It's hard to believe there was a time when we didn't even run signal integrity analysis. It wasn't always a necessity at the larger nodes of several years ago, but it's absolutely essential in today's processes. So I'm sure every one of you out there has battled SI violations...

Posted to Digital Implementation (Weblog) by Kari on Wed, May 18 2011

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NanoRoute

10nm and 14nm FinFETs Pose Challenges – But Collaboration Brings Solutions

NanoRoute doesn't route multi height design

Five-Minute Tutorial: Why You Should Be Running Early DRC

Simple Steps to Debug DRC Violations Undetected in EDI System

10 Encounter Tips and Tricks You May Not Be Aware Of

Improve Your Productivity With Rapid Adoption Kits (RAKs) for Encounter Digital Implementation (EDI) System and Sign-off Flow

When One Via Just Doesn’t Cut It – Recommended Settings for NanoRoute Including Multi-cut Via Insertion Flows

ARM TechCon Paper: Inside Story of a 20nm Test Chip Tapeout

“In Design” DFM Signoff – the Inside Story

Five-Minute Tutorial: Fixing SI Victim Nets