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NVIDIA,PCB Design

  • Allegro 16.6: Easing PCB Design for Multi-Gigabit/Second Signals

    Got a few picoseconds to spare? If you're a PCB designer working with a multi-Gbit/second serial link interface such as PCI Express 3.0 or a DDR memory interface, maybe not. Two new features in the Cadence Allegro 16.6 PCB design solution - announced today (Sept. 25, 2012) at PCB West - aim to help...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Sep 25 2012
  • CES Provides Wake-Up Call for EDA

    Since consumer electronics is the primary driver for IC and systems design, what happens at the Consumer Electronics Show (CES) should interest the EDA community. Any trends in new consumer devices will point the way to design challenges EDA tools will have to solve. From looking at blogs and media coverage...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Jan 11 2010
  • SPB 16.2 release - Constraint Driven HDI PCB Design Flow

    Today's SPB 16.2 release is significant for the Cadence Allegro and OrCAD families of products, but more importantly, I think it brings a lot of new functionality for PCB designers. I will be talking about the improvements in this release over a few blog posts in coming days and weeks. First and...
    Posted to PCB Design (Weblog) by hemant on Mon, Aug 18 2008
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