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  • using ModelSim/QuestaSim VCD file in RTL compiler

    Hi, I want to use VCD file from QuestaSim 6.0 in RTL compiler to obtain power report. The netlist file I am using in QuestaSim for simulation and VCD file generation is also generated by RTL compiler byt when I run following commands I got no asserted signals in the power result. Does RTL compiler supports...
    Posted to Logic Design (Forum) by dkhan on Tue, Jun 18 2013

    Hi,I am new here. when I use the composer to creat a verilog-Editer,there is a *F said interal error,I want to know what is wrong with that? And how to test a pin not only as an input but also as an output?
    Posted to Functional Verification (Forum) by zs0520 on Thu, Mar 22 2012
  • NCSIM: problem with vcd filesize limit

    Hi, I'm currently working with a vhdl example to check the ability of ncsim to limit the filesize of vcd dumpfiles. For that I set up a simple mux with a testbench, that generates stimuli over 540ms. The following simulation flow results in a 1,7G VCD file: $ ncvhdl -cdslib ./cds.lib -hdlvar ./hdl...
    Posted to Functional Verification (Forum) by hbeck on Mon, Aug 22 2011
  • Error with ncvhdl on "protected" type

    Hi, I am using ncvhdl compiler 08.10-s019. I have been trying to simulate a package with a type that is declared as "protected" which is a part od vhdl 2002 feature. So in command line I tried simulating it as ncvhdl -v200x -messages -work work const_pkg.vhd But i am getting this error: type...
    Posted to Functional Verification (Forum) by Swaroop87 on Fri, Feb 4 2011
  • NCVHDL Compiler

    Hi, I have a problem using NCVHDL compiler in Orcad 10.5. The compilation of VHDL libraries ends with an error saying that "ncvhdl" command is unknown as internal or external command, executable or batch file. What is the problem? Do I have to set some system variables or do something else...
    Posted to Functional Verification (Forum) by wolf82 on Wed, Sep 22 2010
  • Tech Tip: Avoiding "Error! Integer Overflow" With Incisive Simulator

    While simulating a VHDL design with Incisive Simulator, if an integer overflow is detected, the simulation stops with the following error message: Error! integer overflow File: ./test.vhd, line = 13, pos = 11 Scope: :$PROCESS_000 Time: 10 FS + 0 ./test.vhd:13 i := i - 1; Incisive is probably the only...
    Posted to Functional Verification (Weblog) by adua on Wed, Jan 28 2009
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