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NCSim,simvision

  • Re: forcing the creation of a vcd file
    Hi Stephen, Thanks for the reply. I strictly need it to be in VCD format as I am passing this file to analog team so that they can use is to see if there is any problem in the signal change and in the signal itself. Also we use it in the tester to test the chip. If there is any way around to probe the...
    Posted to Functional Verification (Forum) by Sumeet Shresth on Mon, Nov 26 2012

  • Re: forcing the creation of a vcd file
    Hi Stephen, I am trying to create the VCD for the system verilog varible being defined as struct using the following command: probe -create -vcd bench.ydec_i -depth all but I am facing the issue showing the following error: ncsim: *E,DBOBBD: Cannot create VCD probe for bench.ydec_i. I am using the simvision...
    Posted to Functional Verification (Forum) by Sumeet Shresth on Sun, Nov 25 2012

  • Testbench with non-unique module names in sub-blocks
    I have a testbench where I am trying to simulate two separate designs that share some module names within their designs. For example, one is a bus controller and the other is bus master and each has a module named InterfaceIo. When I try to simulate there is a conflict of multiple modules with the same...
    Posted to Functional Verification (Forum) by mattyc on Wed, Apr 14 2010
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