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  • .vp file simulate

    Hello Friends, Can any one tell me how to simulate mixed signal .vp file in NC Sim? I have USB PHY Chip Model(analog + digital) in verilog. This model in .vp formet. Can any one tell me how can i simulate this model in NC Sim. Send me some useful link or steps. Best Regards: Digi0100ever
    Posted to Functional Verification (Forum) by digimind4ever on Sat, Sep 11 2010
  • type parameter override

    Does NC support type parameter overrides? If not, why not? I'm attempting to use an interface wrapper with a typed parameter to pass interfaces to the drivers/monitors. But I get this error during compile: typedef virtual cllp_if #(.DW(16), .EW(6), .AW(14)) cllp_if_t; IfWrapper #(cllp_if_t) if_wrapper;...
    Posted to Functional Verification (Forum) by hab94 on Wed, Jul 21 2010
  • Testbench with non-unique module names in sub-blocks

    I have a testbench where I am trying to simulate two separate designs that share some module names within their designs. For example, one is a bus controller and the other is bus master and each has a module named InterfaceIo. When I try to simulate there is a conflict of multiple modules with the same...
    Posted to Functional Verification (Forum) by mattyc on Wed, Apr 14 2010
  • Facing difficulty in fucntional coverage using NCSim

    Hi All, I am facing some difficulty in implementing the functional coverage using NCSim. I have 2 coverpoints of 3 bins each and one cross of one bin. cp_m: coverpoint m { bins m1; bins m2; bins m3; } cp_w: coverpoint w { bins w1; bins w2; bins w3; } crs : cross cp_m, cp_w { option.cross_auto_bin_max...
    Posted to Functional Verification (Forum) by kolipaka on Tue, Oct 6 2009
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