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NASCUG

TLM Design and Verification: What to See at DAC This Year

If you are attending the Design Automation Conference ( DAC 2012 ) June 4-7 in San Francisco and you are interested in SystemC/TLM driven design and verification, including high-level synthesis, there are a lot of interesting sessions. First, there is a parallel conference going on Saturday and Sunday...

Posted to System Design and Verification (Weblog) by Jack Erickson on Thu, May 31 2012
Virtual Divide and Conquer Enables Fixed Sub-Systems

The 17 th North American SystemC User Group meeting ( NASCUG ), will take place this coming Monday (Feb. 27, 2012) at the DoubleTree Hotel in San Jose, CA. I am on the agenda with a presentation called "Extending Fixed Sub-systems at the TLM Level - Experiences from the FPGA World", in which...

Posted to System Design and Verification (Weblog) by fschirrmeister on Thu, Feb 23 2012
Interested in Low Power, Mixed Signal, SystemC Verification? Here’s What to See at DVCon

DVCon, the premier conference for IC and systems verification, will be held Feb. 27- March 2 at the Doubletree Hotel in San Jose, California. This year's conference makes it clear that functional verification isn't just about digital RTL anymore. In fact, there's quite a bit of content in...

Posted to Industry Insights (Weblog) by rgoering on Mon, Jan 30 2012
DVCon Wrap-Up and Blog Review

The DVCon conference, held Feb. 28-March 3 in San Jose, Calif., was by all appearances a success this year. Major events were well attended and the program had a lot of interesting content. While the Universal Verification Methodology (UVM) was a major focus, this year's program made it clear that...

Posted to Industry Insights (Weblog) by rgoering on Thu, Mar 10 2011
Video: SystemC Update From OSCI Chair Eric Lish

Eric Lish, manager of virtual platforms at Intel's Technology and Manufacturing Group, has been chair of the Open SystemC Initiative ( OSCI ) since October 2009. At the North American SystemC User Group ( NASCUG ) meeting at the DVCon conference Feb. 28, I had the opportunity to do a brief video...

Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 9 2011
UVM Meets SystemC and VHDL in DVCon “Town Hall” Forum

Should the Universal Verification Methodology (UVM) work with SystemC? Should VHDL be extended with the object-oriented capabilities of SystemVerilog? Is it better to have interoperability between languages, or a unified language, or a language-neutral verification methodology? These questions and more...

Posted to Industry Insights (Weblog) by rgoering on Tue, Mar 1 2011
Jim Hogan Keynote: Making Money from SoC Realization

Veteran EDA investor Jim Hogan has a practical interest in system-on-chip (SoC) Realization, and he said so at the start of his keynote speech at the North American SystemC User Group (NASCUG) meeting today (Feb. 28, 2011). "My perspective is how I make money off this," he said. "I'm...

Posted to Industry Insights (Weblog) by rgoering on Mon, Feb 28 2011
Cadence Investment in SystemC Continues -- NASCUG SystemC Day at DVCon

Don't lose touch with what's new in the world of SystemC! Cadence is a long time contributor and sponsor of SystemC initiatives, and that commitment continues to show during next week's SystemC Day and North American SystemC User Group (NASCUG) at DVCon . The conference is being held at the...

Posted to System Design and Verification (Weblog) by Steve Brown on Thu, Feb 24 2011
DVCon SystemC Day Quandry: Need for Third Party TLM IP

Sometimes in the most optimistic of discussions, there is an "elephant in the room" that people don't say much about. Such was the case at the DVCon SystemC Day Feb. 22, where despite strong attendance and upbeat presentations, there was only a small amount of discussion about the need...

Posted to Industry Insights (Weblog) by rgoering on Wed, Feb 24 2010
DVCon SystemC Day – Forging A TLM Design/Verification Flow

Advanced design technologies are of no value unless there's a coherent, workable methodology that supports them. SystemC transaction-level modeling (TLM) has lacked a methodology that goes all the way to silicon without major gaps. Independent verification consultant Brian Bailey filled in some of...

Posted to Industry Insights (Weblog) by rgoering on Tue, Feb 23 2010

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NASCUG

TLM Design and Verification: What to See at DAC This Year

Virtual Divide and Conquer Enables Fixed Sub-Systems

Interested in Low Power, Mixed Signal, SystemC Verification? Here’s What to See at DVCon

DVCon Wrap-Up and Blog Review

Video: SystemC Update From OSCI Chair Eric Lish

UVM Meets SystemC and VHDL in DVCon “Town Hall” Forum

Jim Hogan Keynote: Making Money from SoC Realization

Cadence Investment in SystemC Continues -- NASCUG SystemC Day at DVCon

DVCon SystemC Day Quandry: Need for Third Party TLM IP

DVCon SystemC Day – Forging A TLM Design/Verification Flow