	Login with a Cadence account.
Not a member yet? Create a permanent login account to make interactions with Cadence more conveniennt. Register \| Membership benefits

Get email delivery of the Cadence blog (individual posts).

Popular Tags

Browse All Tags

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Send yourself a copy

Cadence RSS Feeds

Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Send Yourself A Copy

Mixed-Signal,functional verification,low power

CDNLive! 2012 Proceedings – Over 150 User Presentations on Design and Verification

A fantastic resource is available for chip and system designers -- proceedings from five of the CDNLive! Conferences held in 2012. By my count this includes over 150 user-authored presentations given at CDNLive! Silicon Valley (March 12-13), CDNLive! EMEA (May 6-8), CDNLive! Taiwan (July 11), CDNLive...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 9 2013
DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!

In late April, a wealth of information on IC functional verification became available at the DVCon web site . Both papers and slides are now available for dozens of high-quality presentations given at the DVCon 2012 conference, which was held Feb. 27-March 1, 2012 in Santa Clara, California. You can...

Posted to Industry Insights (Weblog) by rgoering on Tue, May 1 2012
Interested in Low Power, Mixed Signal, SystemC Verification? Here’s What to See at DVCon

DVCon, the premier conference for IC and systems verification, will be held Feb. 27- March 2 at the Doubletree Hotel in San Jose, California. This year's conference makes it clear that functional verification isn't just about digital RTL anymore. In fact, there's quite a bit of content in...

Posted to Industry Insights (Weblog) by rgoering on Mon, Jan 30 2012
Incisive Performance Scales to Meet Advanced Node SoC Verification Requirements

Its’ all about RTL simulation. I mean gates. I mean turn-around-time. Project-level productivity. Mixed-signal. Low-power. UVM. And. And. And. … And the reality is that advanced node SoCs are so complex that it is truly about all of these. Our new white paper details a systematic approach...

Posted to Functional Verification (Weblog) by Adam Sherilog on Mon, Jan 30 2012
Applying Digital-Centric Verification Methodologies to Analog

A majority (if not all) SoCs today are mixed signal. Increasingly, the analog and digital portions of the design are inseparable. It is not possible any more to decompose them into separate analog and digital functions. Nothing can be treated as a black box and handed off to the other side. The new world...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Jan 12 2011
Simulation of Voltage Scaling for Dynamic Power Reduction

Some background info: In a previous blog , I introduced: DVFS (Dynamic Voltage and Frequency Scaling), a technique used for Dynamic Power Reduction. RVM (Real Valued Modeling) for efficient simulation of mixed signal SoC with very high speed and efficiency using Cadence DMS (Digital Mixed Signal) offerings...

Posted to Functional Verification (Weblog) by Neyaz on Wed, Jul 22 2009
Using wreals to Simulate Frequency Scaling for Dynamic Power Reduction

Some background info: Taking a quick look at Power dissipation in CMOS: Leakage power is well managed by powering down parts of the design when not in use. This is a well understood problem and can be simulated well in IUS (Incisive Unified Simulator) using CPF (Common Power Format) commands to capture...

Posted to Functional Verification (Weblog) by Neyaz on Wed, Jul 15 2009

Page 1 of 1 (7 items)

Popular Tags

Email

Share

Subscribe

Contact Us

Mixed-Signal,functional verification,low power

CDNLive! 2012 Proceedings – Over 150 User Presentations on Design and Verification

DVCon 2012 Verification Paper Archive – UVM, Low Power, Mixed Signal and More!

Interested in Low Power, Mixed Signal, SystemC Verification? Here’s What to See at DVCon

Incisive Performance Scales to Meet Advanced Node SoC Verification Requirements

Applying Digital-Centric Verification Methodologies to Analog

Simulation of Voltage Scaling for Dynamic Power Reduction

Using wreals to Simulate Frequency Scaling for Dynamic Power Reduction