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Mixed language,VHDL

  • MixedLanguage (Verilog+VHDL) Question

    Hello: I am using ncsim 09.20-s016. I have a VHDL DUT. The testbench top level is VHDL. But, I have a few Verilog modules in the testbench. From one of the Verilog modules, I want to access (monitor) a signal inside the DUT (VHDL). For example, if (top.level_1.level_2.sigout_1 == 1'b1) $display("Posedge...
    Posted to Functional Verification (Forum) by ashfaqh on Thu, Aug 5 2010
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