Cadence.com will be under maintenance from Friday, Oct. 3rd at 6pm (PST) thru Sunday, Oct 5th at 11pm (PST).
Cadence.com login, registration, community posting and commenting functionalities will be disabled.
Home > Community > Tags > Mixed language/VHDL
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Mixed language,VHDL

  • MixedLanguage (Verilog+VHDL) Question

    Hello: I am using ncsim 09.20-s016. I have a VHDL DUT. The testbench top level is VHDL. But, I have a few Verilog modules in the testbench. From one of the Verilog modules, I want to access (monitor) a signal inside the DUT (VHDL). For example, if (top.level_1.level_2.sigout_1 == 1'b1) $display("Posedge...
    Posted to Functional Verification (Forum) by ashfaqh on Thu, Aug 5 2010
Page 1 of 1 (1 items)