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Mixed language,Elaborate

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  • Elaborate Verilog and VHDL mixed language design

    I have VHDL design files and my top module is in Verilog. i am using this command to compile and elaborate the design ncvhdl -work work -messages gate_10.vhd ncvhdl -work work -messages dff.vhd ncvlog -work work -messages lfsr_gate_mixed1.v ncvlog -work work -messages lfsr_tb1.v ncelab -work work -messages...
    Posted to Functional Verification (Forum) by Ruchir on Mon, May 17 2010
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