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Panel: 3D-IC Design Experts Tackle “Practical Issues” in 2.5D and 3D TSV Deployment
3D-IC technology has gone from the "grandiose plans" of several years ago to the "practical issues" of ramping up for widespread deployment, according to one panelist at the Electronic Design Process Symposium (EDPS) April 18, 2013 in Monterey, California. That's a pretty good...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Apr 23 2013
MemCon Keynote: Why Hybrid Memory Cube Will “Revolutionize” System Memory
DDR3 and DDR4 aren't enough - it's time for a "revolution" in system memory that will offer exponential improvements in bandwidth, latency, and power efficiency, according to Scott Graham (right), general manager of Hybrid Memory Cube technology at Micron. In a keynote speech at the...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Sep 19 2012
MemCon Keynote: Cloud, Mobility Disrupt Semiconductor Memory Ecosystem
Do you think memory is a boring, slow-moving technology? That's definitely not the case, according to Martin Lund (right), senior vice president at Cadence and keynote speaker at the MemCon 2012 conference Sept. 18, 2012. Lund asserted that these are "exciting times" for a semiconductor...
Posted to
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by
rgoering
on Tue, Sep 18 2012
User View: “Multi-Mode” Synthesis Approach Includes Power Optimization
Logic synthesis is an indispensible IC design tool, but its value has a lot to do with how it's used. At a recent Synthesis Community Event at Cadence Dec. 8, Laszlo Borbely-Bartis, staff design engineer at Micron, described a concurrent multi-mode and low-power optimization synthesis flow using...
Posted to
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by
rgoering
on Thu, Jan 5 2012
Synthesis User Panel: Power Dominates Front End Design
What challenges are users facing in front-end IC design these days? According to presenters at a Q&A panel session at a Synthesis Community Event at Cadence Dec. 8, power minimization and optimization are at the top of the list. The panel included three user presenters, an ARM executive, and a Cadence...
Posted to
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by
rgoering
on Mon, Dec 19 2011
Flash Memory Summit: New Insights Into the Future of NAND Flash
With deployment in some 5 billion mobile devices worldwide, flash memory has been wildly successful. But where will nonvolatile memory technology go from here, and how much further can it scale? Some answers emerged from three keynote speeches at the Flash Memory Summit August 9. The speakers were Yoram...
Posted to
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rgoering
on Wed, Aug 10 2011
DVCon: Mixed-Signal Designers Cite Verification Challenges and Needs
If you want to know how challenging mixed-signal verification really is, the best thing is to listen to the people in the trenches. A March 3 lunch panel at the DVCon conference, sponsored by Cadence, allowed an attentive audience to do just that. The panel included three users and two vendor representatives...
Posted to
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rgoering
on Sun, Mar 6 2011
Flash Memory Summit: Messages For OEMs And SoC Designers
You didn't have to be a memory expert to come away with some key insights from last week's Flash Memory Summit . The conference had some important messages for anyone designing systems-on-chip, or for that matter any kind of electronic product that has a memory subsystem. The conference was a...
Posted to
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rgoering
on Tue, Aug 24 2010
MemCon Question #2: What Comes After DRAM?
DRAM has been the workhorse of the semiconductor memory market for a long, long time. At the MemCon 2010 conference, I learned that the basic DRAM cell design goes back to 1970 and has changed little since. It may seem somewhat heretical to ask, "What Will Replace DRAM?" but a lively panel...
Posted to
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rgoering
on Tue, Aug 3 2010
User Interview: Forging A Multi-Mode Synthesis Flow
Traditional synthesis flows aren’t keeping up with IC complexity and low-power demands, according to Laszlo Borbely, design engineer at Micron Technology . At the recent CDNLive! Silicon Valley , Borbely discussed a new flow that uses concurrent multi-mode synthesis and low-power optimization based...
Posted to
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by
rgoering
on Wed, Dec 9 2009
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