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Send Yourself A Copy
Metric-driven verification,Incisive
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wreal
New Specman Coverage Engine - Extensions Under Subtypes
This is first in a series of three blog posts that are going to present some powerful enhancements that were added to Specman 12.2 in order to ease the modeling of a multi-instance coverage environment. In this blog we're going to focus on the first enhancement, while the other two enhancements will...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, May 28 2013
Designer View – Using Metric-Driven Verification for Mixed-Signal IP
Can digital verification techniques such as verification planning, coverage metrics, and assertion checking be applied to the analog/mixed-signal world? Yes, according to Pierluigi Daglio, analog verification engineer at STMicroelectronics. In a recorded presentation at the Cadence web site, he shows...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Aug 29 2012
Archived Webinar: Which Verification Coverage Metrics to Use When
What metrics matter most at different stages of the verification process? How can metrics be leveraged to reduce the risk of failures in your IC designs? These questions were answered in a recently archived Cadence webinar that offers a comprehensive primer on the use of code coverage, functional coverage...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Nov 14 2011
Webinar: Bringing Digital Verification Methodologies to Mixed-Signal SoCs
It's fairly straightforward (albeit slow) to verify an analog IP block using a Spice simulator. But when that block goes into a mixed-signal system-on-chip (SoC), and the time comes for chip-level verification, a different approach is needed. A recently archived Cadence webinar shows how advanced...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Sep 28 2011
Planes, Trains and Automobiles: European Seminar Series
A couple of blog posts ago, I talked about the worldwide functional verification seminar series that we've been delivering this year. This has been a successful endeavor by almost any metric, but since it's taken a lot of my team's time and energy I'm continuing to monitor every aspect...
Posted to
Functional Verification
(Weblog)
by
tomacadence
on Wed, Jun 22 2011
A Look at the Ongoing Functional Verification Seminar Series
Being a Marketing guy, one thing that I really enjoy is getting on the road for a big, splashy seminar series. For many EDA companies, that used to be a routine annual event with 30 or 40 locations around the world. We'd split them up and visit perhaps 8 or 10 cities apiece. The pace could be a bit...
Posted to
Functional Verification
(Weblog)
by
tomacadence
on Fri, May 20 2011
The Role of Coverage in Formal Verification, Part 3
.special { font-family: 'Courier New' !important; } In the last post of this series, we will address the last but not least of three key questions to be answered with coverage in formal verification: How good are my formal constraints? (Addressed in Part 1 ) How good is my verification proof...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Mon, Feb 14 2011
The Role of Coverage in Formal Verification, Part 2 Continued…
Recall that three main questions need to be answered to attain coverage in formal verification: Part 1 of this series addressed, "How good are my formal constraints?" In Part 2 we showed debugging of over-constraining with help of examples, addressing the question, "How good is my verification...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Thu, Jan 27 2011
User View: How Metric-Driven Verification Improves ASIC and FPGA Quality
To keep bad chips and boards from going into the field, automatic test equipment (ATE) has to be reliable. That's why Teradyne , a major ATE provider, takes verification quality very seriously. With help from Cadence, Teradyne converted from a "home grown" methodology and made the switch...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Jan 23 2011
What Does Silicon Realization Mean for Verification Engineers?
Last May , I posed a question about what EDA360 means for verification engineers. Yesterday we made an announcement about verification for Silicon Realization that is a big deal. We are delivering a lot of new technology with immediate and high value to verification engineers everywhere. My colleagues...
Posted to
Functional Verification
(Weblog)
by
tomacadence
on Tue, Jan 11 2011
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