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MSV,power shut-off

  • Low-Power Technology Summit Proceedings Now Available

    On October 18, 2012 Cadence held a Low-Power Technology Summit at our San Jose, California headquarters. Experts from Cadence and other leading companies presented the latest low-power design methodologies. Well, it took us a while but you can now view the material via the Low-Power Technology Summit...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, Dec 5 2012
  • Low-Power Design Case Studies: 15 CDNLive! Papers So Far This Year

    CDNLive! is back with a bang in 2012, with very strong support from the Cadence user community worldwide. We're three-quarters the way through the events at the time of writing -- you can see the whole program on www.cadence.com at the CDNLive! 2012 Worldwide page. Proceedings are published so far...
    Posted to Low Power (Weblog) by Pete Hardee on Mon, Sep 17 2012
  • Low-Power Design? Brian Bailey Gets It

    Hats off to Brian Bailey! If you haven't been following his EDA Designline Power Series on eetimes.com you have been missing out. Throughout April, he's been running a pretty comprehensive series of editorials, opinion pieces and contributed articles on the subject of low power design. As he...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, May 2 2012
  • Cadence Customers to Showcase Advanced Low-Power Designs at CDNLive!

    CDNLive! Silicon Valley, taking place at the DoubleTree Hotel in San Jose, CA next week from March 13-14, 2012, brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, Mar 7 2012
  • Friday Fun: Modern Methodology Has Benefits

    In this week's episode of "The Next Generation", the Dante Semi team reviews the project status after adopting many new techniques, such as power shutoff, assertion-based verification, physical synthesis, and multi-supply multi-voltage optimization. It looks like things are going well!...
    Posted to Logic Design (Weblog) by Jack Erickson on Fri, Aug 14 2009
  • When Do You Know You've Saved Enough Power?

    This guest post is by David Weir, Lead Design Engineer at Cadence. His paper, "When do you know you've saved enough power?" was voted best-in-track for Logic Design at CDNLive! 2008 Silicon Valley. In this paper we set out to show how designers can measure and explore the impact of implementing...
    Posted to Logic Design (Weblog) by Team FED on Thu, Apr 2 2009
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