Cadence.com will be under maintenance from Friday, Oct. 3rd at 6pm (PST) thru Sunday, Oct 5th at 11pm (PST).
Cadence.com login, registration, community posting and commenting functionalities will be disabled.
Home > Community > Tags > MSV
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

MSV

  • Analog Coverage Metrics in Mixed-Signal Simulations

    This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I will cover metrics collection from analog circuits during mixed-signal simulation. My previous blogs covered some of the following topics: 1. Basics of dynamic...
    Posted to Low Power (Weblog) by Neyaz on Tue, Oct 5 2010
  • Error Detection for Controlled Voltage Sources and Voltage Scaling

    This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I will cover error detection. My previous blogs covered some of the following topics: 1. Basics of dynamic power management 2. Very brief introduction to RNM...
    Posted to Low Power (Weblog) by Neyaz on Tue, Sep 21 2010
  • Simulation of Voltage Scaling for Dynamic Power Reduction

    This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I'll discuss the simulation of closed-loop voltage scaling for adaptive dynamic voltage and frequency scaling (DVFS). My previous blogs covered some of the...
    Posted to Low Power (Weblog) by Neyaz on Tue, Sep 7 2010
  • 5 Tips to Help You Finish Your Low Power Design Tapeout On Time

    So you're about to start your first low power design. Or second, third, or fourth. As with many tapeouts, you know that with today's tight market windows, most likely the project will go off with a sprinting start (architectural planning), followed by an endurance test (designing and implementing...
    Posted to Low Power (Weblog) by Design4Life on Fri, Aug 27 2010
  • Dynamic Power Management – Closed Loop Voltage Scaling

    This posting is part of a series of blogs on dynamic power management in digital-centric mixed-signal verification environments. In this post, I'll discuss open-loop and closed-loop voltage scaling. In previous blogs, I covered some of the following topics: Basics of dynamic power management Very...
    Posted to Low Power (Weblog) by Neyaz on Tue, Aug 24 2010
  • Power Analysis: When Accurate Isn’t Accurate At All

    The notion that your ability to analyze power dissipation more accurately as your design proceeds down the levels of abstraction from system-level, to RTL, and to gate-level and transistor-level netlist has existed unchallenged for too long. Well, would I be tilting at windmills to challenge it? I could...
    Posted to Low Power (Weblog) by Pete Hardee on Fri, Aug 20 2010
  • A Call For Power-Aware IP Models

    Power intent formats exist to express the design's low power techniques separately from the design's functional description. This promotes portability of the design across different power schemes. So why are most commercial IP providers forced to bury this critical information deep in gate-level...
    Posted to Low Power (Weblog) by Pete Hardee on Tue, Aug 3 2010
  • Cadence and Very Cool Stuff

    One of the very cool things about my job is that I get to see all kinds of new stuff early. I’m privileged to be involved in technology roll outs, and so get to be involved in early discussions with R&D, Product Engineering, and Marketing. And, I gotta tell you, there is very cool stuff coming...
    Posted to Digital Implementation (Weblog) by Rich Owen on Tue, Nov 3 2009
  • Friday Fun: Modern Methodology Has Benefits

    In this week's episode of "The Next Generation", the Dante Semi team reviews the project status after adopting many new techniques, such as power shutoff, assertion-based verification, physical synthesis, and multi-supply multi-voltage optimization. It looks like things are going well!...
    Posted to Logic Design (Weblog) by Jack Erickson on Fri, Aug 14 2009
  • RC Design Explorer: Find the Right Balance of Power and Performance

    By Paul Weil Sr. Product Engineer You might be aware that RTL Compiler has had the ability to synthesize top-down to multi-supply multi-voltages (MSMV) and optimize across them. Lowering voltage levels can be a great way to reduce switching power, but it comes at the cost of reducing performance. As...
    Posted to Logic Design (Weblog) by Team FED on Fri, Jul 24 2009
Page 2 of 3 (22 items) < Previous 1 2 3 Next >