Home > Community > Tags > MMSIM70
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

MMSIM70

  • Cadence environment variable

    Does anybody know which environment set the value of rabsshort used in DC and transient simulation? The simulator engine is spectre. Thanks Regards, S Lim
    Posted to Custom IC Design (Forum) by slim5 on Tue, Dec 20 2011
  • How to use Flash core cell models

    Hello, I'm quite new to use Ultrasim and I'm confused how to take flash core cell model into my test bench. I produce netlist with Virtuoso GUI which includes transistors I'd like to treat like FG-transistors. do I use these .appendmodel.. and .model commands in the test bench or should I...
    Posted to Custom IC Design (Forum) by KaniKune on Tue, Nov 23 2010
  • Re: VerilogA Problem in MMSIM-7.1

    Hi !! I'm having a problem when trying to simulate a verilogA block. Gcc seems to be correctly installed and detected by MMSIM. We're using MMSIM 7.11 and IC5.1.41 (Cadence 2009-2010 IC package - icfb 5.1.0 subversion: 5.10.41.500.6.137) within Linux Fedora 11 and with TSMC 0.18um Design Kit...
    Posted to Custom IC Design (Forum) by Winglet on Fri, May 14 2010
  • .csv output in Spectre

    What is the easiest way to generate .csv format output in Spectre?
    Posted to Custom IC Design (Forum) by dmckenney on Thu, Dec 3 2009
  • VerilogA Problem in MMSIM-7.1

    Hi, I am having a problem to simulate my verilogA files under MMSIM 7.1. They work fine under MMSIM-6.0. In spectreout, I get: ERROR (VACOMP-1008): Cannot compile ahdlcmi module library. Check the log file input.ahdlSimDB/3821_soi12so_Test_Tapeout_Sept09_BinarySearch_veriloga_veriloga.va.BinSearch.ahdlcmi...
    Posted to Custom IC Design (Forum) by gokce on Wed, Jun 3 2009
  • Re: matlab interface and PSF data format

    Is SST2 a cadence proprietary waveform format also? How about the calculator function flow? Has anyone try to use it to interface with matlab?
    Posted to Custom IC Design (Forum) by vlau2 on Wed, Aug 20 2008
  • matlab interface and PSF data format

    I am developing a custom function in Cadence's calculator to do some advance analysis from simulation data. I know how to read cadence's simulation data from matlab (using measure functions), after performing matlab transformation of simulation data, I want to write it back to cadence (possibly...
    Posted to Custom IC Design (Forum) by vlau2 on Tue, Aug 19 2008
  • how to create link between new MMSIM and ADEGXL in IC610

    hi I am having trouble in linking MMSIM and ADEGXL. When I try to run simulation in ADEGXL then it shows me the error “ ADEXL-1613: Following tests use older version of Spectre: sensor: inverter_new:1. Make sure to use MMSIM60 or above for these tests”. So I installed newer version of MMSIM...
    Posted to Custom IC Design (Forum) by ashraf on Tue, Jul 29 2008
Page 1 of 1 (8 items)