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Engineer Video: Best Practices for Mixed-Signal SoC (MS-SoC) Verification
Why is there a need for "best practices" in mixed-signal SoC verification, and what are some of those practices? A presentation at the recent DVCon 2013 conference addressed these questions by showing how Maxim Integrated is bringing digital techniques into mixed-signal verification. Here's...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 27 2013
Get Started on UVM-e with Free Introductory Video Tutorials
One of the many requests that we get from Specman/ e customers is that they would like some basic e tutorials. So, as a first step, Axel Scherer has recently posted 24, very short, byte sized UVM- e basic tutorials . Check them out. These e -based videos are targeted for design and verification engineers...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Thu, May 24 2012
Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification
Seven years ago this month (April 2005) Cadence acquired Verisity, the pioneering verification company that developed the e language and the Specman environment. The acquisition resulted in a paradigm shift in IC verification, setting the stage for reusable verification methodologies, constrained-random...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Apr 24 2012
DVCon Paper: UVM-MS Brings Metric-Driven Verification to Mixed-Signal SoCs
Nearly all systems-on-chip (SoCs) are mixed-signal, and they must all be verified. While digital verification is heavily automated, analog verification is still a manual process, making mixed-signal verification extremely challenging. Can we bring digital verification technology, such as metric-driven...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 12 2012
“Advanced Verification” Book Brings UVM to Mixed Signal, Low Power, Multi-Language
The Accellera Systems Initiative Universal Verification Methodology (UVM) standard is helping design and verification engineers build efficient, reusable test environments. But the current standard doesn't cover everything that verification teams will encounter at advanced nodes. Thus, a new book...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jan 17 2012
Webinar: Bringing Digital Verification Methodologies to Mixed-Signal SoCs
It's fairly straightforward (albeit slow) to verify an analog IP block using a Spice simulator. But when that block goes into a mixed-signal system-on-chip (SoC), and the time comes for chip-level verification, a different approach is needed. A recently archived Cadence webinar shows how advanced...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Sep 28 2011
DAC Panel: Users Describe Mixed-Signal Verification Challenges, Solutions
Should analog/mixed-signal verification be more like digital verification, with separate verification teams, a methodology like the Universal Verification Methodology (UVM), and metric-driven verification (MDV)? Yes, according to three mixed-signal engineers at a panel discussion at the Cadence EDA360...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jun 13 2011
UVM-MS – Metric-Driven Verification for Analog IP and Mixed-Signal SoCs
Metric-driven verification and constrained-random stimulus generation have greatly eased digital functional verification, but have rarely been applied to analog IP or mixed-signal SoCs. That may change with a proposed methodology called Universal Verification Methodology-Mixed Signal (UVM-MS), which...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Feb 10 2011
CDNLive! Silicon Valley 2010 in the Rear-View Mirror
Well, we all survived another very busy CDNLive! event last week. Since I posted a preview beforehand I would be remiss if I didn't let you know what happened. The bottom line is that this was a really good show, with more than forty talks covering a wide range of EDA and EDA360 topics. The majority...
Posted to
Functional Verification
(Weblog)
by
tomacadence
on Tue, Nov 2 2010
A Preview of Verification Sessions at CDNLive! Silicon Valley
As Cadence followers well know, our annual worldwide series of CDNLive! events is a big deal both for us and for our customers. We work hard to get the best talks into the program, combining customer case studies, technical updates from Cadence experts, and the occasional partner presentation. As you...
Posted to
Functional Verification
(Weblog)
by
tomacadence
on Wed, Oct 20 2010
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