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Low-Power ,low power

  • Another Expert’s View on Power Intent and Hierarchy

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    Posted to Low Power (Weblog) by Pete Hardee on Wed, Sep 21 2011
  • An Expert’s View on Power Formats and Methodology

    In the last five years since the introduction of power formats, using a side file to describe power intent such as power domains, power modes and associated interface logic has become the mainstream low power design methodology. This marks great progress toward automating complex low power design techniques...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, Aug 24 2011
  • User View: Low Power Challenges at 40nm and Below

    Low power design is hard enough at 65nm and above, and it poses additional challenges at 40nm and below, according to Alex Kuo, department manager at SoC design firm Global Unichip Corp. As noted in another Cadence Community blog post by Qi Wang, Kuo offered a presentation on low-power design at the...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Jun 21 2011
  • Low Power Design -- Alive and Well at DAC

    Low power design was undoubtedly one of the themes of DAC this year -- especially at the Cadence booth. We drew lively interest on the DAC floor with our low power demo station, which was continuously busy especially on the free Monday. We were showing a new demo explaining how advanced low power techniques...
    Posted to Low Power (Weblog) by Pete Hardee on Tue, Jun 14 2011
  • New Proof Points for CPF-enabled Cadence Low Power Solution

    As the clock for the 48 th Design Automation Conference (DAC) ticks away, we at Cadence are scrambling to put the final touch-up on all our DAC activities. Even though my time is limited, I still would like to highlight the significance of two recent and seemingly unrelated events. First is a post at...
    Posted to Low Power (Weblog) by QiWang on Fri, Jun 3 2011
  • How to Control Power Switch Rush Current

    While there are multiple techniques for reducing power consumption, shutting off power domains is the main method used to reduce leakage power consumption. In power shut-off designs, there are multiple aspects designers need to take care of, including IR drop, turn-on time, rush current, and the number...
    Posted to Low Power (Weblog) by SunilVGokhale on Wed, May 11 2011
  • ARM Keynote: Some Inconvenient Truths About Low-Power Design

    While there have been many advances in low-power IC design, it still involves tough choices and poses difficult questions, according to Rob Aitken, R&D fellow at ARM. Aitken talked about the myths and realities of low-power design in a keynote speech at the recent IEEE Electronic Design Processes...
    Posted to Industry Insights (Weblog) by rgoering on Sun, Apr 17 2011
  • Report from Japan – Quake Brings New Perspective on “Power”

    Back in December, I wrote a blog entry entitled " Perspective on Power - 300 Designers and 20,000 Miles Later... ". After the latest leg of my travels last week, taking our EDA360 Tech on Tour Low Power Symposium on the road to Taiwan and Japan, I intended to write an update to that blog article...
    Posted to Low Power (Weblog) by Pete Hardee on Tue, Mar 15 2011
  • A Look Behind the Si2 CPF 2.0 Release

    The long awaited new version of the Common Power Format, CPF 2.0, was released by the Silicon Integration Initiative ( Si2 ), an industry standards organization, today. Here are several interesting observations from this latest release . First of all, this new release is a big step forward for interoperability...
    Posted to Low Power (Weblog) by Pete Hardee on Tue, Feb 15 2011
  • Power Modeling Standards Effort Aims to Ease IP Integration

    A new standards effort that could ease low-power silicon IP integration is quietly underway at the Silicon Integration Initiative (Si2) Low Power Coalition ( LPC ). Although the LPC is probably best known as the home of the Common Power Format (CPF) originated by Cadence, it actually has a much broader...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 26 2011
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