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Low-Power

  • Low Power Marketing Hype – And What They Don’t Tell You
    Here in the USA, we're just back from the Thanksgiving holiday. This year, I got caught up in "Black Friday," which is the day after Thanksgiving, and one of the biggest shopping days of the year, especially for consumer electronics. I'm afraid to say I was convinced enough by some...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, Nov 30 2011

  • Si2 Interoperability Guide V2.0 Available for Download

    Recently, the Silicon Integration Initiative (Si2) announced the availability of the Interoperability Guide for Power Format Standards V2.0 . This is an important milestone of power format interoperability between IEEE 1801-2009 and the Common Power Format (CPF). This update was triggered by the Si2's...
    Posted to Low Power (Weblog) by QiWang on Mon, Oct 31 2011

  • Si2 Conference: New Directions for Low-Power Standards
    The Silicon Integration Initiative (Si2) Conference Oct. 20 provided an ambitious new roadmap for low power standards. Presentations described the current Common Power Format (CPF) 2.0 release, steps towards interoperability with IEEE 1801 (Universal Power Format, UPF), a new approach to power modeling...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Oct 24 2011

  • Cadence Low Power Guru Wins Si2’s Distinguished Service Award

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    Posted to Low Power (Weblog) by Pete Hardee on Fri, Oct 21 2011

  • Another Expert’s View on Power Intent and Hierarchy
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    Posted to Low Power (Weblog) by Pete Hardee on Wed, Sep 21 2011

  • An Expert’s View on Power Formats and Methodology
    In the last five years since the introduction of power formats, using a side file to describe power intent such as power domains, power modes and associated interface logic has become the mainstream low power design methodology. This marks great progress toward automating complex low power design techniques...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, Aug 24 2011

  • User View: Low Power Challenges at 40nm and Below
    Low power design is hard enough at 65nm and above, and it poses additional challenges at 40nm and below, according to Alex Kuo, department manager at SoC design firm Global Unichip Corp. As noted in another Cadence Community blog post by Qi Wang, Kuo offered a presentation on low-power design at the...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Jun 21 2011

  • Low Power Design -- Alive and Well at DAC
    Low power design was undoubtedly one of the themes of DAC this year -- especially at the Cadence booth. We drew lively interest on the DAC floor with our low power demo station, which was continuously busy especially on the free Monday. We were showing a new demo explaining how advanced low power techniques...
    Posted to Low Power (Weblog) by Pete Hardee on Tue, Jun 14 2011

  • New Proof Points for CPF-enabled Cadence Low Power Solution

    As the clock for the 48 th Design Automation Conference (DAC) ticks away, we at Cadence are scrambling to put the final touch-up on all our DAC activities. Even though my time is limited, I still would like to highlight the significance of two recent and seemingly unrelated events. First is a post at...
    Posted to Low Power (Weblog) by QiWang on Fri, Jun 3 2011

  • How to Control Power Switch Rush Current
    While there are multiple techniques for reducing power consumption, shutting off power domains is the main method used to reduce leakage power consumption. In power shut-off designs, there are multiple aspects designers need to take care of, including IR drop, turn-on time, rush current, and the number...
    Posted to Low Power (Weblog) by SunilVGokhale on Wed, May 11 2011
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