Home > Community > Tags > Low-Power /CPF/Functional Verification
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Low-Power ,CPF,Functional Verification

  • Your First Low-power Verification Project - Webinar

    So your team just specified its first design with power management circuits. The designers are telling you, its just a few power shut-off domains defined by CPF or UPF. The verification should be easy-peasy right? Wrong. Each domain has complete controls, isolation, and retention. As a verification engineer...
    Posted to Low Power (Weblog) by Adam Sherilog on Thu, Oct 11 2012
  • Low-Power Verification With SystemC - The Great Unknown

    Design teams have used C/C++/SystemC reference models for many years and the trend is growing with SystemC synthesis. At the same time, many teams are adding power-aware structures to their designs and trying to simulate. So what happens when the models encounter unknowns propagated from shutdown blocks...
    Posted to Functional Verification (Weblog) by Team genIES on Thu, Jan 28 2010
  • Are You Playing with a Full Deck?

    A professional gambler confidently place bets because she know the odds, but she would be crazy to play at a table that didn’t use a full deck because the odds change in an unknown way. If you use a simulator that doesn’t enable low-power verification in every test run, you are just as crazy...
    Posted to Functional Verification (Weblog) by Team genIES on Tue, Dec 15 2009
Page 1 of 1 (3 items)