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Low power ,UPF

  • What’s Cool for Low-Power at DAC?

    Low-power design promises to be a key theme of the Design Automation Conference once again! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), if you need to cover design, implementation and verification of this important subject, there's a lot to choose from at Cadence's...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, May 30 2012
  • Low-Power Design? Brian Bailey Gets It

    Hats off to Brian Bailey! If you haven't been following his EDA Designline Power Series on eetimes.com you have been missing out. Throughout April, he's been running a pretty comprehensive series of editorials, opinion pieces and contributed articles on the subject of low power design. As he...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, May 2 2012
  • System-Level Low Power Design – What Will it Take to Move There?

    While many low-power design techniques are available to IC designers, the greatest potential for power savings is at the system level, where both software and hardware can be considered. So what's standing in the way of system-level low power design, and what needs to happen to make it practical...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Apr 18 2012
  • DVCon User Panelists: Is Low Power Design Worth the Costs?

    Much has been written about the specific techniques that IC designers can use for low-power design and verification, but a larger context is missing. What's the end goal, and what are the costs, benefits, and challenges of implementing power management? In a lively panel discussion at the DVCon conference...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Feb 29 2012
  • What’s Next in Low Power?

    Low power has become a major consideration in chip design in almost all applications. One major achievement of the industry over the past a few years is the alignment on the low power design methodology, which was considered as the biggest hurdle to automate advanced low power design techniques. No matter...
    Posted to Low Power (Weblog) by QiWang on Tue, Jan 24 2012
  • Si2 Interoperability Guide V2.0 Available for Download

    Recently, the Silicon Integration Initiative (Si2) announced the availability of the Interoperability Guide for Power Format Standards V2.0 . This is an important milestone of power format interoperability between IEEE 1801-2009 and the Common Power Format (CPF). This update was triggered by the Si2's...
    Posted to Low Power (Weblog) by QiWang on Mon, Oct 31 2011
  • Si2 Conference: New Directions for Low-Power Standards

    The Silicon Integration Initiative (Si2) Conference Oct. 20 provided an ambitious new roadmap for low power standards. Presentations described the current Common Power Format (CPF) 2.0 release, steps towards interoperability with IEEE 1801 (Universal Power Format, UPF), a new approach to power modeling...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Oct 24 2011
  • Cadence Low Power Guru Wins Si2’s Distinguished Service Award

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    Posted to Low Power (Weblog) by Pete Hardee on Fri, Oct 21 2011
  • Another Expert’s View on Power Intent and Hierarchy

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    Posted to Low Power (Weblog) by Pete Hardee on Wed, Sep 21 2011
  • Low-power Keeps Gate-Level Simulation Forever Young

    Ann Mutschler blogged in the Low-Power Engineering Community that gate-level simulation is coming back, driven in part by low-power verification needs. “In a small sense, what’s old is new” may actually be the biggest understatement in her blog. Ann attributes the observation to Cadence’s...
    Posted to Low Power (Weblog) by Adam Sherilog on Thu, Sep 8 2011
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