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Low power ,RTL compiler
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Power Difference between Analog Simulation and RTL complier estimation
Hallo, I am creating a standard cell library. I did analog simulation for cell design and estimated power values for the cells , lets say, NOT, NOR and NAND and I have their power values for static, dynamic, etc. Now based on that I created library file, and used that in RTL omplier for single cell designs...
Posted to
Logic Design
(Forum)
by
GreenGraphene
on Mon, Mar 25 2013
Margins are Costly - Don't Let Them Grow Out of Control!
Last week, Professor Jan Rabaey of the University of California at Berkeley gave a great keynote at Cadence's Low Power Technology Summit that called for changes to the conventional solutions for power reduction. One of the points he made was that today's designs are over-designed and over-constrained...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Wed, Oct 24 2012
Designer View – Low-Power IC Design Challenges and Solutions
The IC physical design team at Marvell Technology Group Ltd. has a tough challenge. They're under a lot of pressure to minimize power consumption as much as possible, while getting products out the door quickly. In a recorded presentation at the Cadence web site, Murali Natarajan, senior physical...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Aug 23 2012
User View: “Multi-Mode” Synthesis Approach Includes Power Optimization
Logic synthesis is an indispensible IC design tool, but its value has a lot to do with how it's used. At a recent Synthesis Community Event at Cadence Dec. 8, Laszlo Borbely-Bartis, staff design engineer at Micron, described a concurrent multi-mode and low-power optimization synthesis flow using...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jan 5 2012
Synthesis User Panel: Power Dominates Front End Design
What challenges are users facing in front-end IC design these days? According to presenters at a Q&A panel session at a Synthesis Community Event at Cadence Dec. 8, power minimization and optimization are at the top of the list. The panel included three user presenters, an ARM executive, and a Cadence...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Dec 19 2011
How Logic Synthesis is Changing
You probably haven't read much about logic synthesis lately -- it's a mature technology that doesn't attract much attention. But that doesn't mean that new and exciting things aren't happening in synthesis and front-end design, as illustrated by presentations at a Synthesis Community...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Dec 14 2011
RC info message
Hi , When I am inserting my low pwer cells using RTL Compiler I am getting info as "Global Inversion not done". Can any one tell me what is meaning of this. Below is the log file message. Info : Enabled level shifter inserted. [CPF_ISO-204] : Enabled level shifter inserted at port: 'xyz'...
Posted to
Logic Design
(Forum)
by
PradyK
on Wed, Sep 21 2011
8 Users Compare RTL Compiler (RC) vs. Design Compiler (DC) on DeepChip.com
It was refreshing to see what happened when John Cooley made his latest request for reader feedback on his popular DeepChip website catering to the semiconductor design community. A request had come in from a previous DeepChip post prior to the Design Automation Conference (DAC) as follows: Are there...
Posted to
Logic Design
(Weblog)
by
David Stratman
on Mon, Jun 20 2011
Tackling your Greatest Chip Design Challenges with the Cadence Digital End-to-End Flow
It hasn't been that long, but do you recall your new year's resolution? Eat healthier? Have more work-life balance? Exercise more? Or, what about, "create a chip that is so compelling and useful, it blows everybody's socks off in the semiconductor industry?" If the latter is your...
Posted to
Digital Implementation
(Weblog)
by
Design4Life
on Mon, Jan 31 2011
Q&A Interview: Nimish Modi Describes Front End ‘Paradigm Shift’
Nimish Modi is senior vice president for front end research and development at Cadence. In this interview, he discusses Cadence’s front end strategy in such areas as low power, mixed signal, system development, enterprise verification and predictive design. He also explains why he thinks EDA technology...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Aug 10 2009
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