Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
3D-IC
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
More Products
OrCAD Products
Sigrity Technologies
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
The Fuller View Blog
Quicklinks
All Blogs
All Forums
Community Search
CDNLive User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> Low power /DAC/Industry Insights
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
The Fuller View Blog
All Blog Categories
Popular Tags
Allegro
Analog
ARM
cadence
DAC
Digital Implementation
e
EDA360
encounter
ESL
functional verification
Incisive
industry insights
Low power
mixed-signal
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
TLM
UVM
verification
Virtuoso
Browse All Tags
Email
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Share
Twitter
Facebook
LinkedIn
Google+
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
Low power ,DAC,Industry Insights
14nm
1801-2013
2(x)nm
20nm
20nm tools
28nm
32 bit
3D
3D IC
3D ICs
3D-IC
8 bit
8051
Accellera
AMS
Analog
analog modeling
analog/mixed-signal
ARM
ARM Cortex-M0
ARM CTO
ARM1
ASIC
assertions
automotive electronics
behavioral modeling
Biggs
Cadence
Cadence at DAC
Cadence breakfast
Cadence demos
Chian
ChipEstimate
Choi
cloud
collaboration
common power format
Conformal Low Power
Cortex-M
Cortex-M0
CPF
custom
custom/analog
DAC 2011
DAC 2012
DAC 2013
DAC breakfast
DAC demo suites
DAC keynote
DAC lunch
DAC lunches
DAC panel
data management
demo suites
Design Automation Conference
design rules
DF
DFM
digitally-assisted analog
DVFS
ECO
EDA
EDA360
EDA360 Theater
EDI
electrically-aware design
Encounter Digital Implementation
energy harvesting
ESL
fabless
Faraday
FinFET
foundry
Freescale
Freescale CEO
Global Foundries
Global Unichip
GlobalFoundries
Gregg Lowe
IP
microcontrollers
mixed signal
Mixed-Signal
NXP
OpenPDK
Power
power formats
power management
RC
RF
RF verification
RTL
RTL Compiler
SaaS
Samsung
scaling
Schulz
semiconductor scaling
Si2
verification
DAC 2013: Accellera Panel Updates Power Format Standards
In what was billed as a "town hall meeting" about the new IEEE 1801-2013 (UPF 2.1) power intent format standard , the Accellera Systems Initiative sponsored a breakfast panel at the Design Automation Conference ( DAC 2013 ) Monday, June 3. The discussion took a broader look at power intent...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jun 6 2013
Freescale CEO at DAC 2013: “Internet of Things” Brings Opportunities, Challenges
The "Internet of Things" has become a common buzzword, but what potential does it bring, and what design challenges must be overcome to create it? Freescale president and CEO Gregg Lowe has done some serious thinking about these issues, and he shared his thoughts in an entertaining keynote...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jun 3 2013
Designer View – Low-Power IC Design Challenges and Solutions
The IC physical design team at Marvell Technology Group Ltd. has a tough challenge. They're under a lot of pressure to minimize power consumption as much as possible, while getting products out the door quickly. In a recorded presentation at the Cadence web site, Murali Natarajan, senior physical...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Aug 23 2012
Panel: Integrating Low-Power ARM Processors into Mixed-Signal Designs
Mixed-signal chip designs with embedded digital signal processing are becoming more and more commonplace these days. How can you bring low-power processors, such as the ARM Cortex-M0 , into such designs quickly and efficiently? A lunch panel discussion at the recent Design Automation Conference (DAC...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jun 20 2012
DAC 2012 Panelists: How to Succeed at 28nm, 20nm and 14nm
What will it take to achieve silicon success at 28nm and below? That was the question put to a panel of experts at a Cadence-sponsored breakfast at the Design Automation Conference ( DAC 2012 ) June 6, where speakers from IBM, Cadence, ARM, Samsung, and GLOBALFOUNDRIES shed new light on business and...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jun 12 2012
ARM CTO at DAC 2012: The Truth About Semiconductor Scaling
As process nodes shrink, semiconductor scaling more or less follows the predictions of Moore's Law - but there are some surprising twists and turns. In a keynote speech at the Design Automation Conference ( DAC 2012 ) June 5, Mike Muller, co-founder and CTO of ARM, compared the original ARM1 processor...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jun 6 2012
Mixed-Signal Methodology Guide Sets New Directions for SoCs
Nearly all systems-on-chip (SoCs) these days are mixed-signal, with increasingly complex analog/mixed-signal (AMS) IP blocks. Meanwhile, analog blocks increasingly contain digital control logic. Yet analog and digital design are still done in relative isolation, using very different methodologies and...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, May 30 2012
12 Hot EDA Topics – 78 DAC Demo Sessions
Whatever your role in the chip or system design process, there is probably a Cadence demo geared to your interests at the Design Automation Conference ( DAC 2012 ) June 3-7 in San Francisco. Cadence has three demo suites at its booth (#1930) and is running one-hour demos from 10:00 am to 5:00 pm Monday...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, May 24 2012
Free DAC Lunches: Custom/Analog Variability, ARM Low Power Processors in Mixed-Signal Designs
There is such a thing as a free lunch - if you're at the 49th Design Automation Conference (DAC) in San Francisco June 3-7. Cadence is sponsoring two lunches at which you can learn about two important technology topics - custom/analog variability, and the use of ARM processors in low-power, mixed...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, May 14 2012
Si2’s Steve Schulz: “Setting the Standards for EDA360”
EDA360 represents a significant change in which the EDA industry plays a broader role in the creation of hardware/software systems ready for applications deployment. A shift this profound must be rooted in industry standards, according to Steve Schulz, president of the Silicon Integration Initiative...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jun 27 2011
Page 1 of 2 (16 items) 1
2
Next >