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User View: Going “Green” With Low-Power Design and Clock Concurrent Optimization (CCOpt)
Network processing chips are tough to design. They're big, they're fast, and they have to minimize power consumption. At CDNLive! Silicon Valley 2012 (the Cadence user group conference) Ranjit LoboPrabhu, physical design manager at Netronome Systems , shared some ways his company is going "green"...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Apr 4 2012
Where There's Smoke, There's fire in the Belly of an Aspiring Engineer
Humans learn with their hands and, it turns out, electrical engineers are humans. Most of us fondly recall "experiments" we did that made electrical engineering our destiny. But what of the current generation? Have apps deadened the EE in the way video killed the radio star? I am happy to report...
Posted to
Low Power
(Weblog)
by
Adam Sherilog
on Mon, Apr 2 2012
CDNLive! -- The Other Side of the Low Power Design Techniques
In a recent CDNLive! Silicon Valley presentation titled "Low Power Implementation on the Freescale Kinetis Family," Annis Jarrar from Freescale demonstrated how various low power design techniques were used in the popular Kinetis low power platform. These techniques included power gating with...
Posted to
Low Power
(Weblog)
by
QiWang
on Thu, Mar 29 2012
CDNLive! Keynote – New Horizons for ARM Based SoCs
30 billion ARM-based chips have shipped over the last 20 years, but ARM isn't stopping there. ARM is looking beyond cell phones and mobile devices and pursuing new opportunities in the server, home entertainment, and automotive marketplaces, according to Tom Lantzsch (right), executive vice president...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Mar 15 2012
Photo Essay, Video Playlist, and Comments on DVCon 2012
In addition to the annotated image gallery (click here or on the image), or the playlist of videos on some of the papers, panels, partner activities, and tutorials ((click here or on the composite image), below are some long form comments on particular aspects of this year's Design & Verification...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Mon, Mar 12 2012
DVCon 2012 Video: Product Engineer Chris Komar Reviews the Tutorial on Formal Apps
In this interview Product Engineer Chris Komar recaps the tutorial on formal apps given on Thursday March 1, 2012 at DVCon. Chris outlines how the "apps" approach can tackle verification challenges that are relatively easy for formal and formal+simulation to solve, and backs this up with some...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Thu, Mar 8 2012
Join EDA “Movers and Shakers” at IEEE EDP Symposium – Cloud, 3D-ICs, Power and More
If you want a deeper understanding of the challenges, trends, and potential new solutions for IC and systems design, there's no better place to find out than the IEEE-sponsored Electronic Design Processes Symposium (EDP) April 5-6, 2012, in Monterey, California. Now in its 19 th year, this interactive...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Mar 8 2012
Cadence Customers to Showcase Advanced Low-Power Designs at CDNLive!
CDNLive! Silicon Valley, taking place at the DoubleTree Hotel in San Jose, CA next week from March 13-14, 2012, brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing...
Posted to
Low Power
(Weblog)
by
Pete Hardee
on Wed, Mar 7 2012
Learn How to Do Mixed-Signal Design at CDNLive! Silicon Valley
With the theme of Connect, Share and Inspire, this year's CDNLive! Silicon Valley March 13-14, 2012 will be an exciting forum for Cadence customers to share their most recent chip design successes and learn from each other. Among close to 100 presentations during the packed two day agenda, one area...
Posted to
Mixed-Signal Design
(Weblog)
by
QiWang
on Wed, Mar 7 2012
EDA CEOs Speak Out: 3D-ICs, IP Integration, Low Power, and More
What's driving the EDA industry today and where is it headed in the near future? Some high-level answers to these questions came from the EDA Consortium (EDAC) annual CEO Forecast panel Feb. 29, 2012. EDA industry leaders shared their views about 3D-ICs, SoC integration, power management, industry...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 5 2012
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