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Logic synthesis,Physical timing closure

  • The Dangers of Excessive Guard Banding

    By Matt Rardon Synthesis Solutions I want to take a couple of minutes to talk about guard banding of constraints in logic synthesis. This approach was initially conceived to add a little bit of padding to the design to account for inaccuracies in synthesis modeling techniques and to provide some wiggle...
    Posted to Logic Design (Weblog) by Team FED on Thu, Apr 16 2009
  • Where Oh Where is "number_of_routing_layers"?

    OK, I'll just do " set_attribute number_of_routing_layers 6 "... Error : The attribute is read-only. [TUI-26] [set_attribute] : attribute: 'number_of_routing_layers', object type: 'root' : Cannot set or reset read-only attributes. Hey, wait a minute! If you are faced with...
    Posted to Logic Design (Weblog) by mrardon on Wed, Mar 18 2009
  • Blogs: What interests you? What do you want to read about?

    With the new blogging opportunities at Cadence, is there anything you'd like to read more about for frontend design? Stuff like: Early chip-planning/prototyping, synthesis (including physical-synthesis), formal verication, DFT, frontend methodologies, etc. My hope is for the blog topics to be informative...
    Posted to Logic Design (Weblog) by Kenneth Chang on Mon, Sep 15 2008
  • "What is ChipEstimate?" plus a touch of RC-Physical x 2

    Day 2 @ CDNLive San Jose: Another interesting day - met quite a few people, some new, others I met the day before while co-presenting at two morning sessions, and also some of my fav customers. My focus-of-the-day - ChipEstimate awareness with a touch of RC-P. Here are some attendees' feedback: Question...
    Posted to Logic Design (Weblog) by Kenneth Chang on Thu, Sep 11 2008
  • Logic Handoff Models at 45nm and Beyond

    CDNLive! Silicon Valley has been a good conference so far, lots of good papers and conversations. One thing I wanted to share was a panel discussion yesterday entitled "Logic Handoff Models at 45nm and Beyond." It was a great discussion, moderated by Ron Wilson of EDN, and on the panel were...
    Posted to Logic Design (Weblog) by Jack Erickson on Wed, Sep 10 2008
  • Feeling Restless ... CDNLive San Jose Conference Update!

    Ah yes ... my first blog here! I can't believe the freedom we're getting at Cadence, unfiltered blogging. :) I co-authored and helped deliver two presentations/papers yesterday with a couple of down-to-earth engineers. Thanks to everyone who was able to attend these sessions, it was fun meeting...
    Posted to Logic Design (Weblog) by Kenneth Chang on Wed, Sep 10 2008
  • Logic Design at CDNLive! Silicon Valley -- see you Sept. 8!

    We've been working hard to put together another CDNLive! event, coming up September 8-11 in San Jose. There is a whole track dedicated to Logic Design. Some of the events I'll be working at are: Sept 8. at 8am: Techtorial " Achieve Project Success Through Early Low-Power Planning and Validation"...
    Posted to Logic Design (Weblog) by Jack Erickson on Wed, Aug 27 2008
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