Home > Community > Tags > Logic Design/rtl compiler 8.1
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Logic Design,rtl compiler 8.1

  • Where Oh Where is "number_of_routing_layers"?

    OK, I'll just do " set_attribute number_of_routing_layers 6 "... Error : The attribute is read-only. [TUI-26] [set_attribute] : attribute: 'number_of_routing_layers', object type: 'root' : Cannot set or reset read-only attributes. Hey, wait a minute! If you are faced with...
    Posted to Logic Design (Weblog) by mrardon on Wed, Mar 18 2009
  • Are You Guilty of "Synthesis Inertia"?

    By Jason Ware Sr. Technical Leader Team FED Inertia is the resistance of an object to a change in its state of motion. (Wikipedia). Are you guilty of staying with synthesis scripts that were written when we were still in the Cold War? Well, maybe its time to "tear down the wall" and start fresh...
    Posted to Logic Design (Weblog) by Team FED on Thu, Mar 5 2009
  • Changes to Cadence RTL Compiler PLE Mode with 8.1 release

    RC-Physical has two major components to it: PLE (Physical Layout Estimate) which is a model to better represent physical capacitance during optimization; and Synth -to_placed which runs a full placement, trial route and optimization. This change affects PLE ONLY, there is no change to Synth -to_placed...
    Posted to Logic Design (Weblog) by Jason Ware on Fri, Sep 26 2008
Page 1 of 1 (3 items)