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Logic Design,logic low power design

  • DesignWare and AmbitWare Demystified - Why and When to Avoid?

    By Diego Hammerschlag Sr. Technical Leader Team FED Most, if not all, synthesis tools today support the use of Synopsys DesignWare or a vendor specific brand of <vendor>Ware such as Ambit's AmbitWare, Cadence's ChipWare and others. I have been frequently asked on the purpose of <vendor>Ware...
    Posted to Logic Design (Weblog) by Team FED on Fri, Jul 24 2009
  • Don't Let Power Kill Your Project - What % LVT Should I Use?

    By Diego Hammerschlag Sr. Technical Leader Team FED A common question or requirement that designers have is the percentage of low voltage threshold (LVT) cells that should be allowed in a design. For those not familiar with LVT cells, they are special cells that have a lower voltage threshold and can...
    Posted to Logic Design (Weblog) by Team FED on Wed, May 13 2009
  • The Dangers of Excessive Guard Banding

    By Matt Rardon Synthesis Solutions I want to take a couple of minutes to talk about guard banding of constraints in logic synthesis. This approach was initially conceived to add a little bit of padding to the design to account for inaccuracies in synthesis modeling techniques and to provide some wiggle...
    Posted to Logic Design (Weblog) by Team FED on Thu, Apr 16 2009
  • Don't Let Power Kill Your Project

    By Diego Hammerschlag Sr. Technical Leader Team FED Power has gone from an imminent threat to the cause of multiple projects across several vendors going under. I have heard of multiple projects that had working RTL prototypes and were far into the backend flow only to find out that the power used would...
    Posted to Logic Design (Weblog) by Team FED on Tue, Mar 31 2009
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