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Logic Design

  • Tips for Fixing Timing Violations and Adopting Best Practices for Optimization with RTL Compiler

    Best Practices for Optimization What should be my considerations while preparing data? Libraries, HDL, Constraints... A good result from a synthesis tool depends greatly on the input data. An old saying "garbage in garbage out" is also true for RTL Compiler. Before attempting to run synthesis...
    Posted to Logic Design (Weblog) by SumeetAggarwal on Tue, Aug 7 2012
  • Boost Productivity With Synthesis, Test and Verification Flow Rapid Adoption Kits (RAKs)

    A focus on customer enablement across all Cadence sub-organizations has led to a cross-functional effort to identify opportunities to bring our customers to proficiency with our products and flows. Hence, Rapid Adoption Kits -- RAKs -- for Synthesis, Test and Verification Flow were born! What is a RAK...
    Posted to Logic Design (Weblog) by SumeetAggarwal on Tue, Jul 24 2012
  • RTL compiler - synthesis

    I am traying to synthesize a design to a library with no basic inverters. In general, RTL compiler requires inverters and some other basic cells. and so i will recieve : "synthesis failed- do not have usable inverters". My library have all the logical veriaty of cells except a straight forward...
    Posted to Logic Design (Forum) by Ivan13 on Sun, Jan 15 2012
  • RTL Compiler: Does coding style influence synthesis result?

    Hi, A specific cominational function can be coded in several ways. (See examples below) (1) Will different HDL implementations be synthesized differently ? (2) If (1) is true, are there any guidelines of which coding style is better ? for example - Find First Set module FFS_1(input wire [2:0] i, output...
    Posted to Logic Design (Forum) by Tzachi Noy on Thu, Jun 23 2011
  • 8 Users Compare RTL Compiler (RC) vs. Design Compiler (DC) on DeepChip.com

    It was refreshing to see what happened when John Cooley made his latest request for reader feedback on his popular DeepChip website catering to the semiconductor design community. A request had come in from a previous DeepChip post prior to the Design Automation Conference (DAC) as follows: Are there...
    Posted to Logic Design (Weblog) by David Stratman on Mon, Jun 20 2011
  • Power Net Extraction Problem in Abstract Generator

    Halo, I am creating abstract cell views for a digital standard cell library using Cadence Abstract Generator.I have the following problem: In the Extract Step, I set the tool up to extract signal and power nets and to create pins on metal 1 so that my abstract view will keep its connectivity. The extract...
    Posted to Custom IC Design (Forum) by eklikeroomys on Mon, Mar 14 2011
  • Going 'Digital End-to-End' ... and Riding Your ECOs to the Finish Line

    Thinking of your next ASIC ECOs? It could be for today, or maybe you are considering your next ASIC ECO methodology. You are probably not alone ... most designs will go through ECOs , whether they are related to bug fixes (those 'oh oh' moments of silence), or intended functional changes (which...
    Posted to Logic Design (Weblog) by Kenneth Chang on Mon, Feb 7 2011
  • naming on CSA module

    Hi: I have a datapath module, after synthesize -to_generic, there are some CSA module has been added by RC, which naming is very ugly. Both in module name and instance name. its RTL is :assign mout_int = smult(coeff,datain); where smult is a function. and its instance name is : \smult_30_22:mux_59_9_g1...
    Posted to Logic Design (Forum) by tompy on Wed, Jan 5 2011
  • PART TABLE FILE CHANGES

    For Part Table Files with large amount of package types (i.e. res & caps), when a value is changed or a part is added, regardless if the part is in a project, HDL is notifying and forcing the user to update their schematic when these parts are not even used in their given design. This adds a lot...
    Posted to PCB Design (Forum) by Jonah Stephenson on Thu, Aug 19 2010
  • Model Libraries

    I am trying to simulate a simple inverter using nmos, and pmos in Analog_Parts library but the netlist doesn't get created because of the model libraries, both of these transistors have only 3 legs, is there a .scs file to add or a different type of model libraries, where can I find such a file?
    Posted to Logic Design (Forum) by Musmar on Wed, Jun 30 2010
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