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Logic Design,chip estimate

  • Q&A: Michał Siwiński Sees Major Shift in Product Design and Verification

    The rising costs of product development are causing fundamental changes in the design and verification flows, according to Michał Siwiński, group director of front-end product management at Cadence. In this interview he discusses customer challenges and Cadence strategies in such areas as hardware/software...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 6 2010
  • Ah, Power! Now Can I Drive?

    Last week a large number of customers and potential customers attended the “System-level Design & Chip Architecture for Low-Power ICs Techtorial and Workshop” sessions in Irvine, San Diego, and San Jose. They must have been monitoring sub-space communication channels or read this blog...
    Posted to Logic Design (Weblog) by Mike Carrell on Fri, Apr 24 2009
  • Frontend Design and Verification Trends for 2008 - A Personal AE Perspective

    Each year, before I head off into vacation mode at the end of the year, I like to think back to what I learned through trends, to drive my 2009 personal goals and expectations. In a nutshell, here's my view from visiting a large number of customers in North America, mostly in the San Jose area: Chip...
    Posted to Logic Design (Weblog) by Kenneth Chang on Fri, Dec 26 2008
  • When Green Chips Turn Brown

    I went to New York City last weekend and went to see a Broadway show called Avenue Q. It's a very adult adaption of Sesame Street (sort of). Before you grab a bus, plane, or train to NYC to see this show with your kids, be forewarned. Puppets aside, this is NOT a show for children. And while that...
    Posted to Logic Design (Weblog) by jflieder on Thu, Nov 20 2008
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