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Logic Design,chip design,ASIC

  • How to Make Your Chip Fail: Part II ...

    Working at Cadence for 2 years has given me a lot of experience with many different customers and their flows. It's what I looked forward to after working at 4 other companies as a designer who developed flows (since setting up an ASIC flow is fun, playing with all kinds of vendor tools (feeling...
    Posted to Logic Design (Weblog) by Kenneth Chang on Fri, Nov 14 2008
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