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Logic Design,ECO

  • Going 'Digital End-to-End' ... and Riding Your ECOs to the Finish Line

    Thinking of your next ASIC ECOs? It could be for today, or maybe you are considering your next ASIC ECO methodology. You are probably not alone ... most designs will go through ECOs , whether they are related to bug fixes (those 'oh oh' moments of silence), or intended functional changes (which...
    Posted to Logic Design (Weblog) by Kenneth Chang on Mon, Feb 7 2011
  • User Panel: Can Formal Tools Reduce Need For Simulation?

    It was not surprising that a customer Q&A panel at the Logic Design Technology Event, held at Cadence last week, would focus almost entirely on functional verification. As one panelist noted, verification consumes over 50 percent of the design effort. What I found interesting was the amount of discussion...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Nov 16 2009
  • How-to Plans for ECOs - Advice From Experts

    By Bassilios Petrakis I often wonder whether designers plan out well in advance their ECO methodology and strategy for a project. For instance, how do they determine how many spare gates to add, what type, where to place them, how to connect them. Or, what is the impact of RTL coding style, aggressive...
    Posted to Logic Design (Weblog) by Team FED on Thu, Oct 15 2009
  • Friday Fun: A Last-minute ECO

    In this week's episode, the Dante Semi team is about to tape out when they get a last minute spec adjustment from their primary customer. Does this sound familiar? How will they make the change and verify it quickly enough to be able to tape out on time? (Hint: Conformal ECO ). Enjoy! If video fails...
    Posted to Logic Design (Weblog) by Jack Erickson on Fri, Sep 4 2009
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