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Logic Design

  • What Can We Learn From The iPad About Chip Design?

    You probably heard that Apple announced a touchscreen tablet computer last week. The announcement came with a lot of talk of it defining a new product category. That's somewhat laughable, since tablet computers have been around for a few years. BUT - the previous tablet computers were all based on...
    Posted to Logic Design (Weblog) by Jack Erickson on Tue, Feb 2 2010
  • RTL-to-GDSII Does Not Need Re-tooling - It Needs Re-definition!

    I recently saw a blog post written by a competitor on a purportedly neutral EDA blog, that called for a re-tooling of the RTL-to-GDSII flow. The argument was that for designs 20M gates or larger, you needed to synthesize at the chip-level, and synthesize in conjunction with placement. It also goes on...
    Posted to Logic Design (Weblog) by Jack Erickson on Mon, Jan 25 2010
  • Q&A: Michał Siwiński Sees Major Shift in Product Design and Verification

    The rising costs of product development are causing fundamental changes in the design and verification flows, according to Michał Siwiński, group director of front-end product management at Cadence. In this interview he discusses customer challenges and Cadence strategies in such areas as hardware/software...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 6 2010
  • My Wish List For The New Decade

    Okay, it's the holiday season and end of the year, so I'll combine it all and make a wish list for the new year (as it relates to chip design). Heck, it's the end of the decade - so why not make a wish list for the new decade? A decade is a long time in our industry. This year, my 7-year...
    Posted to Logic Design (Weblog) by Jack Erickson on Tue, Dec 29 2009
  • Need help with VHDL libraries in RTL Compiler

    I have an VHDL file that I want to synthesize that starts like this: library ieee; use ieee.std_logic_1164.all; library grlib;(this is a library I define) use.grlib.amba.all; ... when I synthesize with RTL Compiler, it will give me an error like this: "use.grlib.amba.all", no such primary unit...
    Posted to Logic Design (Forum) by yqzhang on Wed, Dec 16 2009
  • Attention RTL Compiler Customers! RC 9.1.200 Is Here

    Cadence's synthesis R&D team has an early holiday gift for our RTL Compiler customers. The 9.1.200 release (or as our release management system affectionally calls it, "RC9.1-s203") is now available for download. This release is mainly focused on improvements to the core synthesis engine...
    Posted to Logic Design (Weblog) by Jack Erickson on Tue, Dec 15 2009
  • User Panel: Can Formal Tools Reduce Need For Simulation?

    It was not surprising that a customer Q&A panel at the Logic Design Technology Event, held at Cadence last week, would focus almost entirely on functional verification. As one panelist noted, verification consumes over 50 percent of the design effort. What I found interesting was the amount of discussion...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Nov 16 2009
  • Reg .VCD file generation

    Hi, I need to run power analysis . so i need .vcd file. So can any ione say how to generate a .vcd file. I have model sim, Xilix, RC compiler , SoC Encpunter 8.1 . From these can i generate a .vcd file if so let me know the steps pla.. i have lib, lef , sdc, sdf.etc file swith me.. plz help me.. i need...
    Posted to Logic Design (Forum) by Music on Wed, Nov 11 2009
  • How Much Power Are You Leaving On The Table?

    Everybody is looking to reduce their chip's power consumption these days. Often a lot of reduction is needed in order to fit in the desired power envelope. Until now, designers of chips for wireless applications formed the majority of the power management community. These days, it is applicable to...
    Posted to Logic Design (Weblog) by Jack Erickson on Fri, Oct 23 2009
  • Physically-Aware Synthesis: This Time it’s Different

    RTL Compiler Physical has been available for about 2 years now, and we're getting more customers all the time. But we still get the question - how is this different from physical synthesis tools like PKS or Physical Compiler? Those of you that were around 10 years ago when physical synthesis was...
    Posted to Logic Design (Weblog) by Jack Erickson on Fri, Oct 16 2009
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