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Logic Design

  • Going 'Digital End-to-End' ... and Riding Your ECOs to the Finish Line
    Thinking of your next ASIC ECOs? It could be for today, or maybe you are considering your next ASIC ECO methodology. You are probably not alone ... most designs will go through ECOs , whether they are related to bug fixes (those 'oh oh' moments of silence), or intended functional changes (which...
    Posted to Logic Design (Weblog) by Kenneth Chang on Mon, Feb 7 2011

  • naming on CSA module
    Hi: I have a datapath module, after synthesize -to_generic, there are some CSA module has been added by RC, which naming is very ugly. Both in module name and instance name. its RTL is :assign mout_int = smult(coeff,datain); where smult is a function. and its instance name is : \smult_30_22:mux_59_9_g1...
    Posted to Logic Design (Forum) by tompy on Wed, Jan 5 2011

  • PART TABLE FILE CHANGES
    For Part Table Files with large amount of package types (i.e. res & caps), when a value is changed or a part is added, regardless if the part is in a project, HDL is notifying and forcing the user to update their schematic when these parts are not even used in their given design. This adds a lot...
    Posted to PCB Design (Forum) by Jonah Stephenson on Thu, Aug 19 2010

  • Model Libraries
    I am trying to simulate a simple inverter using nmos, and pmos in Analog_Parts library but the netlist doesn't get created because of the model libraries, both of these transistors have only 3 legs, is there a .scs file to add or a different type of model libraries, where can I find such a file?
    Posted to Logic Design (Forum) by Musmar on Wed, Jun 30 2010

  • RTL Compiler synthesis problem, memory ports not mapped!!! Generated memory macrocells unusable!!!
    Hello, I am facing a problem during the synthesis (RTL Compiler) which I cannot solve. Here is the problem: Initial status: 1) I have coded my digital design in VHDL. 2) The code has been simulated successfully. 3) In my digital design I also need SRAM and ROM macrocells. a. So I used the ARTISAN memory...
    Posted to Logic Design (Forum) by albares on Wed, Jun 30 2010

  • Getting Warning X library error detected while trying to open gui for CCD
    I am getting the following warning while trying to switch to the GUI mode in Encounter Conformal Constraint Dessigner(CCD) SETUP> set gui on // Switching to GUI mode X library error detected: 3 - BadWindow (invalid Window parameter) The gui is opening after the warning but it hangs. How can this be...
    Posted to Logic Design (Forum) by rgaddh on Wed, Jun 2 2010

  • EDA360: Enlightenment for Silicon Test
    At a macro level EDA360 is about driving the semiconductor industry toward sustainable differentiation. It represents a Cadence mission to help its customers' customers achieve industry leadership and profitability through enabling technologies, methodologies, and services. Ultimately it is a charter...
    Posted to Logic Design (Weblog) by Ed JM on Fri, May 21 2010

  • CDNLive! EMEA: Taking logic design beyond the imagination
    With a tagline of "Go beyond your imagination", it was pretty clear that this year's CDNLive! EMEA event would not be a typical user conference. Of course it also kicked off just days after our EDA360 launch, so there was a lot of buzz around that. Cadence's CMO, John Bruggeman, kicked...
    Posted to Logic Design (Weblog) by Jack Erickson on Thu, May 6 2010

  • Enabling Profitable Silicon Production: A Learning ‘Neural’ Network for Yield Ramp
    It can not be overstated that the continued health of the chip industry hinges on profitable nanometer production, which depends on yield ramp and yield gap closure. The widening yield gap -- the difference between actual and predicted yield -- and its impact on profitability has far-reaching implications...
    Posted to Logic Design (Weblog) by Ed JM on Thu, Apr 29 2010

  • The new ChipEstimate.com: The place to be for IP
    If you are not yet familiar with the ChipEstimate.com site.....first, why not? It is the leading portal for design IP with over 200 IP suppliers and over 8,000 components available. The team behind the site has been hard at work making it an even more compelling destination for all things IP. For instance...
    Posted to Logic Design (Weblog) by Jack Erickson on Wed, Apr 21 2010
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