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Library,Logic Design

  • Re: Asynchronous FIFO design

    Hi, You should view video tutorial about that topice you should found excellent tutorial on it.
    Posted to Logic Design (Forum) by KennyWylies on Sun, Oct 27 2013
  • RTL compiler - synthesis

    I am traying to synthesize a design to a library with no basic inverters. In general, RTL compiler requires inverters and some other basic cells. and so i will recieve : "synthesis failed- do not have usable inverters". My library have all the logical veriaty of cells except a straight forward...
    Posted to Logic Design (Forum) by Ivan13 on Sun, Jan 15 2012
  • PART TABLE FILE CHANGES

    For Part Table Files with large amount of package types (i.e. res & caps), when a value is changed or a part is added, regardless if the part is in a project, HDL is notifying and forcing the user to update their schematic when these parts are not even used in their given design. This adds a lot...
    Posted to PCB Design (Forum) by Jonah Stephenson on Thu, Aug 19 2010
  • Model Libraries

    I am trying to simulate a simple inverter using nmos, and pmos in Analog_Parts library but the netlist doesn't get created because of the model libraries, both of these transistors have only 3 legs, is there a .scs file to add or a different type of model libraries, where can I find such a file?
    Posted to Logic Design (Forum) by Musmar on Wed, Jun 30 2010
  • RTL Compiler synthesis problem, memory ports not mapped!!! Generated memory macrocells unusable!!!

    Hello, I am facing a problem during the synthesis (RTL Compiler) which I cannot solve. Here is the problem: Initial status: 1) I have coded my digital design in VHDL. 2) The code has been simulated successfully. 3) In my digital design I also need SRAM and ROM macrocells. a. So I used the ARTISAN memory...
    Posted to Logic Design (Forum) by albares on Wed, Jun 30 2010
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