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  • What's Good About Allegro PCB Editor Generic Cross-Section Files? See for Yourself in 16.6!

    Beginning with the Allegro PCB Edito r 16.6 release, you are provided a methodology to export a technology (.tcf) or constraints (.dcf) file which is a generic cross-section. A generic-cross-section file (GCSF) captures constraints for specific layer types. Currently, a GCSF supports four types of layers...
    Posted to PCB Design (Weblog) by Jerry GenPart on Tue, Apr 9 2013
  • naming of dummy instances

    Greetings Forum, 1st time poster : I have been using this code to rename my dummy instances which works fine the first time I use this but subsequent runs report that "DUMMY0" already exists. How to modify this to remember where it left off last time? One idea I had was parsing the current...
    Posted to Custom IC SKILL (Forum) by Malcolmw on Mon, Mar 18 2013
  • What's Good About Allegro PCB Editor Place Replicate Text Support? Check Out 16.6!

    The Allegro PCB Editor Place Replicate application now supports the processing of component reference designators. The work performed in customizing assembly text or silkscreen to the seed circuit can now be leveraged across the replicated modules. Read on for more details… In the image below...
    Posted to PCB Design (Weblog) by Jerry GenPart on Mon, Mar 4 2013
  • What's Good About OrCAD Capture’s Signal Integrity Flow? The Secret's in the 16.6 Release!

    With the 16.6 release, you now have the capability of utilizing the PCB SI tools (SigXP) to work with topologies and constraints in the OrCAD Capture environment. Capturing constraints early in design cycle is important for the following reasons: Quality challenges as the design cycle for any PCB product...
    Posted to PCB Design (Weblog) by Jerry GenPart on Tue, Feb 19 2013
  • How to convert metal1 to metal2

    Hi All, Is there any way ( skill code ) to convert the metal1 to metal2 in Virtuoso Layout Suite. I will select metal1 in the layout and using a BindKey, can I convert it to metal2 or viceversa?? I am using Layout L Suite and Cadence Virtuoso 6.1.4. version. Thanks in Advance! Thanks, Baig.
    Posted to Custom IC SKILL (Forum) by Siddique baig on Fri, Feb 15 2013
  • umc 180 nm LVS with Calibre

    First I must say I must not sure if this should be asked here or Mentor's forums, anyways because I have used this forum before I will fire it up here... While using Virtuoso for custom layout on UMC 180 and trying LVS check with Calibre I have a problem with ports. In theory that should be easy...
    Posted to Custom IC Design (Forum) by soathana on Wed, Feb 13 2013
  • How to get the windowId?

    Hi all, I am new to skill. Could anyone please explain me how to get the windowId ? geOpen( ?window w_windowId ?lib t_lib ?cell t_cell ?view t_view ?viewType t_viewType ?mode t_mode ) => t / nil I have all the required information such as lib name, cell view, view type and mode, but I am struggling...
    Posted to Custom IC Design (Forum) by Siddique baig on Wed, Feb 6 2013
  • What's Good About RF PCB and Layout? 16.6 Has Many New Enhancements!

    The 16.6 Allegro RF PCB application has many new enhancements. I’ll cover a few over the next several weeks. Here are some major layout related enhancements: Snap Enhancements Add Connect Enhancements Modify Connectivity Enhancements Add Component Enhancements Scaled Copy Enhancements Single Segment...
    Posted to PCB Design (Weblog) by Jerry GenPart on Tue, Dec 11 2012
  • Translating a Layout PCB, character length

    Good morning all, I tried to translate an old board, but some footprints get the "_" removed from the name. I believe this is because the names are more than 31 characters. I know how to change this in a design, but do not know how to/or if it can be changed in the translater. Any help would...
    Posted to PCB Design (Forum) by KEN13 on Thu, Nov 29 2012
  • PCB Design and Layout

    Hi all, I am really stuck in the following problem, please help me... When we import a circuit drawn in the ORCAD Schematic into the ORCAD Layout with necessary Netlist, does the connection integrity (even in cases where the interconnecting lines as seen in the layout as soon as they are imported) is...
    Posted to PCB Design (Forum) by Wonderman on Tue, Nov 20 2012
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