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Layout

  • PR Boundary
    Hello, When drawing layout from schematic, there is a PR Boundary option in the 'Generate All From Source' dialog box. It is depicted as a cyan field, that covers other layers. Placing a transistor (or ony other cell) on it makes it invisible (the PR boundary covers it). What is its purpose and...
    Posted to Custom IC Design (Forum) by pitter on Mon, Nov 16 2009

  • How to modify a automatically generated instance.
    Hi, After inductor cell generation (done with Passive Component Designer - PSD) I made DRC check, that found errors in the layout schematic. The problem is that some vias are placed too near to the edge of the polysilicon Patterned Ground Shield - PGD. I tried to remove the vias or correct the layout...
    Posted to RF Design (Forum) by pitter on Thu, Nov 5 2009

  • What is the syntax for creating pins withing SKILL
    I tried accessing the documentation, but it seems to be unavailable at my university this year. I was just wondering what the syntax for creating a pin is. I think it is dbCreatePin( ) but i don't know the parameters. Also is there a way to specify what material/metal the pin is created on?
    Posted to Custom IC Design (Forum) by JMCaJHU on Wed, Sep 16 2009

  • Irregular Footprints in Layout Plus and/or Help Migrating Design to Allegro PCB Editor
    Greetings all- I'm trying to use the following RF connector, Radiall R222508000, in a design I'm working on: http://radiall.applixia.net/catalogue/resource?path=PRODUCT/PDF/TDS/coaxialconnectors/R222508000EN.pdf It has irregular pad shapes in the footprint. I've designed the board in Layout...
    Posted to PCB Design (Forum) by cwparker on Thu, Aug 13 2009

  • Loss of plane connectivity
    I just recently updated from OrCAD version 14.2 to 16.2. I translated a completed 4-layer design from Layout to PCB Editor.When I open the design in PCB Editor, I have lost all of the connections to the inner plane layers and copper pour areas on the outer layers and all of the power and ground nets...
    Posted to PCB Design (Forum) by ddchar on Thu, Aug 13 2009

  • How To Find 1 Unrouted Net?
    I am using OrCAD PCB Editor v16.2 and I have a design that has 1 unrouted net out of 366 nets. I can't find where this unrouted net is. I started by looking for the rats nest, but it doesn't show up. I assume it is a very small disconnect that is difficult to find. Does anyone know a way to find...
    Posted to PCB Design (Forum) by melview1 on Wed, Jul 22 2009

  • [SOC Encounter] ERROR (cannot malloc)
    I have a problem in running SOC Encounter. During the 'optDesign -preCTS' (after placement), Encounter is terminated with this message >Nr of prerouted/Fixed nets = 1164 >routingBox: (200 400) (26039800 26039600) >coreBox: (620000 620000) (25420000 25420000) >**ERROR: (SOCSYUTIL-15...
    Posted to Digital Implementation (Forum) by Yusuf on Wed, Jul 15 2009

  • IC613 crash issue
    Hi, I am using IC613 to create a layout and every time I try to create an instance, it says - "LE-107016 Cannot create a recursive instance placement" even though its not recursive - I created a new library and new cell view. I then click "OK" and continue to create my instance, but...
    Posted to Custom IC Design (Forum) by govilv on Fri, Jun 26 2009

  • Generating .lib file from layout
    Hi, I am trying to generate my own .lib file from the layout I've designed in Virtuoso. I tried to use SignalStorm, but figured out that I do not have license for it. Could anyone please suggest any other tool to do this? Also, does SignalStorm come along with the standard university package? I remember...
    Posted to Custom IC Design (Forum) by govilv on Mon, Jun 22 2009

  • saveDerived in Assura doesn't work
    Hi, I am trying to generate fill structures using Assura DRC and therefore want to output the derived layer to somewhere. I am trying to use the saveDerived rule to save it to the extracted view: saveDerived( m2fill ("m2fill" "drawing" ) ext_view ) But nothing happens. I tried copyGraphics...
    Posted to Custom IC Design (Forum) by janko on Fri, Jun 19 2009
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