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Layout,Virtuoso

  • Virtuosity: 15 Things I Learned in December 2013 by Browsing Cadence Online Support

    With this month's title, I'll need to start adding the year, as this marks the one-year anniversary of the montly series. I know it's been a useful monthly exercise for me. Hopefully it has been helpful for everyone out there as well. Application Notes 1. How to Utilize a Windowing Technique...
    Posted to Custom IC Design (Weblog) by stacyw on Fri, Jan 17 2014
  • Parasitic extraction of standalone metal traces (IC6.1.5)

    Hi, I have a layout view with multiple metal traces adjacent to one another that I want to simulate as an array of resistors/capacitors. Is there a way to obtain the exact resistance/capacitance of these metal traces through parasitic extraction? I'm assuming there has to be some sort of linking...
    Posted to Custom IC Design (Forum) by Wes8 on Mon, Jan 6 2014
  • SKILL for the Skilled: SKILL++ hi App Forms

    One way to learn how to use the SKILL++ Object System is by extending an application which already exists. Once you understand how extension by inheritance works, it will be easier to implement SKILL++ applications from the ground up. I.e., if you understand inheritance, you can better architect your...
    Posted to Custom IC Design (Weblog) by Team SKILL on Mon, Dec 2 2013
  • Virtuosity: 16 Things I Learned in September by Browsing Cadence Online Support

    Rapid Adoption Kits By now, I think you know what RAKs are, and that they include a detailed instructional document and database. Use the title link above to access the main landing page and browse all the available material. 1. DRD-based Interactive Compactor The DRD-based interactive compactor can...
    Posted to Custom IC Design (Weblog) by stacyw on Fri, Oct 11 2013
  • Accessing MultiPart Path (MPP) subpart attributes using itkDB

    Hello. I'm trying to retrieve information about multipart paths in a C++ program using CDBA functions. I am able to identify MPP master path and corresponding ROD attributes (name, system/user handles, choppability, etc.). It is also possible to get a list of MPP sub-shapes. But it's unclear...
  • IBIS model simulation

    I am designing a Data acquisition system with a Texas instruments ADC, Inamps and a ST micro electronics micro controller. I am getting spice models for my inamps, differential amplifiers etc. so that I could do SPICE simulation. I wish to see the output of my ADC if I am providing an input signal with...
    Posted to PCB Design (Forum) by niranjan madha on Wed, Apr 17 2013
  • Virtuoso Layout: instance boundry

    Hello everybody, I sometimes see a strange behaviour when creating a layout in IC6.15: Starting at some time (do not know when/why) doing a fit does fit the layout in the middle of the layout editor, but there is a huge black area around it. So the size of the layout (rectangle form) shown is <<50...
    Posted to Custom IC Design (Forum) by MarkusK on Wed, Apr 10 2013
  • User View: A 20nm Custom IC Constraint-Driven Flow

    If the semiconductor industry is going to ramp up for 20nm design, a custom IC flow that can handle this process node is essential. This flow will require more automation than previous nodes. In a recorded audio presentation at the Cadence web site Francois Lemery, member of the Technology R&D group...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Jul 25 2012
  • Running Cadence IC on VMware?

    My IT department is very enthusastic about putting everything on VMware. They say that this will make their job much easier. I would like to know if you, anyone, or your company has tried running Cadence IC, ADE, or Virtuososo (any version) on VMware and how it worked out for you.
    Posted to Custom IC Design (Forum) by John Reeder on Fri, Apr 6 2012
  • Cadence crash !

    Hi, I have just installed a new PDK on my CADENCE IC 6.1.4, and I have the following errors that I cannot solve! : 1/ When I launch cadence IC6.1.4 with the command: "virtuoso", I can see in the CIW window that the initialization runs a lot of time and finally ends with : " * Error * unknown...
    Posted to Custom IC Design (Forum) by lraf on Fri, Aug 26 2011
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