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Layout,LVS

  • User View: A 20nm Custom IC Constraint-Driven Flow

    If the semiconductor industry is going to ramp up for 20nm design, a custom IC flow that can handle this process node is essential. This flow will require more automation than previous nodes. In a recorded audio presentation at the Cadence web site Francois Lemery, member of the Technology R&D group...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Jul 25 2012
  • High frequency quadrature VCO design with good phase noise

    Hello everyone I am a newbie engineer starting my career in RF IC design and working on designing a high frequency VCO (38 GHz) with good phase noise characteristics. I am using Cadence IC6.1.5-64b.500 version and spectre simulator for the schemtic design and simulations. I have to do everything from...
    Posted to Custom IC Design (Forum) by rohan kr on Thu, Mar 29 2012
  • Any way to Abort Assura LVS run after input layers read ?

    We have a process with multiple variations that include slightly different input layers. To handle the variations within the same LVS file, we have switches. However, if a user is running process variation A and accidentally chooses the swtich to run variation B (having different input layers) , is there...
    Posted to Custom IC Design (Forum) by jm3395 on Wed, Mar 23 2011
  • vdd not sensed in post-layout simulation

    Hi, I tried to do post layout simulation with extracted, symbolized inverter, however, I got the message during simualtion: Notice from spectre during topology check. Only one connection to node 'vdd!' I plot the output and confirmed that vdd is not applied to the internal transistors of the...
    Posted to Custom IC Design (Forum) by Malolo on Tue, Jan 12 2010
  • Custom Inductor | INDDEF layer | HitKit | Assura

    Hi, this post isin reference to http://www.cadence.com/community/forums/T/14022.aspx , where i described problems concerning an inductor that had been automatically generated by VPCD tool. Defining the layout of the inductor as a blackBox does not solve the problem, for assura does not recognize pins...
    Posted to Custom IC Design (Forum) by pitter on Tue, Dec 1 2009
  • VXL - forcing conectivity of existing nets

    Hi, I had a Designer do some modification to a layout I created. They basically reordered a few devices for better matching. Now I find that the devices have been renamed but the metal paths connecting them have the old names and VXL is refusing to enable the 'Show Incomplete Nets' functions...
    Posted to Custom IC Design (Forum) by DCrampton on Wed, May 27 2009
  • LVS Problem with Artist Flat Netlisting

    Hello, I encountered a LVS problem a week ago. I searched this forum before I post but I think my LVS problem is unique. Here is a section of the error log Begin netlist: Mar 27 11:49:11 2009 view name list = ("auLvs" "extracted" "schematic") stop name list = ("auLvs"...
    Posted to Custom IC Design (Forum) by weiz on Mon, Mar 30 2009
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