Home > Community > Tags > Layout/Assura
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Layout,Assura

  • Running Cadence IC on VMware?

    My IT department is very enthusastic about putting everything on VMware. They say that this will make their job much easier. I would like to know if you, anyone, or your company has tried running Cadence IC, ADE, or Virtuososo (any version) on VMware and how it worked out for you.
    Posted to Custom IC Design (Forum) by John Reeder on Fri, Apr 6 2012
  • Any way to Abort Assura LVS run after input layers read ?

    We have a process with multiple variations that include slightly different input layers. To handle the variations within the same LVS file, we have switches. However, if a user is running process variation A and accidentally chooses the swtich to run variation B (having different input layers) , is there...
    Posted to Custom IC Design (Forum) by jm3395 on Wed, Mar 23 2011
  • Custom Inductor | INDDEF layer | HitKit | Assura

    Hi, this post isin reference to http://www.cadence.com/community/forums/T/14022.aspx , where i described problems concerning an inductor that had been automatically generated by VPCD tool. Defining the layout of the inductor as a blackBox does not solve the problem, for assura does not recognize pins...
    Posted to Custom IC Design (Forum) by pitter on Tue, Dec 1 2009
  • How to modify a automatically generated instance.

    Hi, After inductor cell generation (done with Passive Component Designer - PSD) I made DRC check, that found errors in the layout schematic. The problem is that some vias are placed too near to the edge of the polysilicon Patterned Ground Shield - PGD. I tried to remove the vias or correct the layout...
    Posted to RF Design (Forum) by pitter on Thu, Nov 5 2009
Page 1 of 1 (4 items)