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  • cdl export error when lvs with dracula

    Hi everybody... cdl export error when lvs with dracula.error:unable to descend into any of the views defined in the view list :“aucdl schematic” for instance I120 in the cell mult4.But I do not find the I120 in the schematic .After I corrected some instances the error appeared. Thanks
    Posted to Custom IC Design (Forum) by kobe0704 on Tue, Dec 7 2010
  • vdd not sensed in post-layout simulation

    Hi, I tried to do post layout simulation with extracted, symbolized inverter, however, I got the message during simualtion: Notice from spectre during topology check. Only one connection to node 'vdd!' I plot the output and confirmed that vdd is not applied to the internal transistors of the...
    Posted to Custom IC Design (Forum) by Malolo on Tue, Jan 12 2010
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