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LVS,IC6

  • DIVA LVS Error

    Forum users, I've created a schematic and layout of a simple cell using IC6.1.0 and trying to perform DIVA LVS by invoking it from the Virtuoso Layout L window by selecting Verify->LVS... I am getting an error that I think signifies that the layout is failing to netlist. Please see attached figure...
    Posted to Custom IC Design (Forum) by saullacour on Mon, Apr 23 2012
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