Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
3D-IC
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
More Products
OrCAD Products
Sigrity Technologies
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
Quicklinks
All Blogs
All Forums
Community Search
CDNLive User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> LEF
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
All Blog Categories
Popular Tags
Allegro
Analog
ARM
cadence
DAC
Digital Implementation
e
EDA360
encounter
ESL
functional verification
Incisive
industry insights
Low power
Mixed-Signal
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
TLM
UVM
verification
Virtuoso
Browse All Tags
Email
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Share
Twitter
Facebook
LinkedIn
Google+
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
LEF
.lib
6.1.3
abstract
Add Route Routing Standard Cells
Altos Liberate
blog
Brian Wallace
cadence
cadence 6.1 virtuoso
Cadence Online Support
cell view encounter cell layout
characterization
congestion trial route overflow
createPGPin
current density
debug DRC violations
DEF
design rules
detailRoute
Digital Implementation
DRC
DRC signoff
DRC violations
ecounter
EDI
EDI system
EM
encounter
Encounter pre-routes DRC violations
Encounter Digital Implementation
Encounter ECO
Encounter Layout Simulation VDD! GND! Global Signals
encounter power system
Encounter-Metal Fill
EPS
five minute tutorial
globalRoute
IR Drop
IRdrop
layout
LEF abstract generation databse units
LEF to OpenAccess
lefOut followpins
library
low power
Mapfile
mixed signal
mixed-signal
multi height cell
NanoRoute
nanoroute encounter routing
nanoroute faraday crash global detail routing
OA
OpenAccess
output load
PDK
placeDesign
PnR
power
power analysis
power-grid views
PVS
QRC
rail analysis
route
routing
rtl compiler
SDC constraints
soc encounter
SOCe
SoC-Encounter
source script RC
Special route
sroute globalnetconnect
standard cells
Techfile
tf LEF tech
tlf
Verify Geometry
Verilog Encounter Synthesize synthesis digital matrix crossbar
Virtuoso
Warnings NanoRoute
IRdrop Analysis
Hi, I am going to do both static and dynamic IRdrop analysis. During static analysis I encountered a problem. I need LEF-Tech Map file. Would you please describe me how I can get this file. By the way, If you have any tutorial on IRdrop analysis and the flow of this process, I'd appreciate if you...
Posted to
Digital Implementation
(Forum)
by
yazdan
on Fri, Oct 7 2011
RULE LEF_DEFAULT definition for Abstract Generator/Encounter/NanoRoute
I am using Cadence Abstract Generator to create abstract cell views for a standard cell library. In the Verify Step, I keep getting the following error: Encounter: (NRDB-158) There is no default via from LAYER MET1 to LAYER MET2 in RULE LEF_DEFAULT. I do not know how or where to define this RULE LEF_DEFAULT...
Posted to
Custom IC Design
(Forum)
by
eklikeroomys
on Tue, Mar 15 2011
lef unit confusion
Hello there, I'm a bit confused with LEF unit: I've a LEF file with DATABASE MICRONS 2000 ; However, the LEF/DEF language reference interprets one LEF distance unit as multiplied when converted into database units. In other words, if for a LAYER M1 WIDTH 0.10 ; , does this mean that the actual...
Posted to
Digital Implementation
(Forum)
by
Holdsworth
on Mon, Sep 13 2010
createPGPin to the rescue: getting the power pins you want in your block LEF
Hi Everyone! Welcome to my first blog post! My plan for this space is to share with you various tips and tricks in SoC-Encounter as well as new things I learn along the way. I use Encounter every day as part of my job in Cadence Design Services. Knowledge is a two-way street, so I'm hoping that we'll...
Posted to
Digital Implementation
(Weblog)
by
Kari
on Fri, Oct 10 2008
Page 2 of 2 (14 items)
< Previous
1
2