Home > Community > Tags > LEF
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

LEF

  • Default Load in RTL Compiler

    I am creating Standard Cell library. I have generated my own library file. I havent included LEF in the RTL compiler. . 1 )When i estimate power my RTL compiler does produce a result but I am uncertain of which load it is assuming d what toggle rate or stimuli is being considered... . 2) I want to set...
    Posted to Digital Implementation (Forum) by GreenGraphene on Thu, Mar 28 2013
  • Re: IC5141 - LEFOut failed.

    Hi, I managed to generated the LEF file of a simple design. What i do is to added prRules section into the techfile. Yeah! But, the output lef is has only technology information. All design related info such as MACRO, SITE is missing from the left file. Do i need to add any property like prCellType and...
    Posted to Custom IC Design (Forum) by kb how on Tue, Mar 5 2013
  • Five-Minute Tutorial: Create Encounter Power System (EPS) Power-Grid Views For Standard Cells

    In today's tutorial, I'm giving you a sample EPS (Encounter Power System) script that you can use to generate power-grid views for your standard cells. Power-grid views are used during rail analysis, with IR-Drop and EM (electromigration/current density) being the two most popular analysis types...
    Posted to Digital Implementation (Weblog) by Kari on Fri, Feb 22 2013
  • NanoRoute doesn't route multi height design

    Hello, as a test case I have a mixed design with 4 rows only. 3 standard core cell rows and 1 second row, that has a multiple of standard cell row height & pitch. Site definition is done properly. The design contains 2 cells only, one per each row. I created the floorplan, defined the globalNetConnect...
    Posted to Digital Implementation (Forum) by scudex on Wed, Feb 6 2013
  • Transitioning Your LEF-Based EDI System Design Flow to OpenAccess

    The trend of combining analog and digital circuits on a single chip has been growing for several years. More recently I'm seeing more and more designers improve their productivity by transitioning their designs to Open Access (OA) and taking advantage of the interoperability between Virtuoso and...
    Posted to Digital Implementation (Weblog) by wally1 on Mon, Nov 12 2012
  • Simple Steps to Debug DRC Violations Undetected in EDI System

    You've placed and routed your design in the Encounter Digital Implementation (EDI) System. It passed Verify Geometry and Verify Connectivity without a violation. Great! But when you run DRC signoff with your physical verification tool, you have violations related to the routing. What should you do...
    Posted to Digital Implementation (Weblog) by wally1 on Mon, Sep 10 2012
  • Generating LEF from layout view

    Hi all! I have been trying to export LEF from standard cells layout in order to use that LEF file in Encounter for automatic PnR. From virtuoso I select File -> Export -> LEF and fill the form appropriately but the lefout.log is giving a warning on metal 4 as shown below: Warning (OALEFDEF-50144...
    Posted to Custom IC Design (Forum) by BraveHeart on Tue, Jun 12 2012
  • getting a tech LEF from tech .tf format [Encounter 10.11]

    Hi all, I am trying to import my gate level netlist to encounter tool and it asks for Technology LEF file but i have been supplied with file in .tf format. Is there any way to convert this .tf in LEF or to use .tf file directly in the tool. Thanks, Nishith
    Posted to Digital Implementation (Forum) by nisshu on Wed, Feb 15 2012
  • SOC Encounter :: LEF File load Failed

    Hi I am using SoC Encounter 10.1. While importing the design I load the netlist file (i.e. *.v file) and then add the LEF file to the list. When I press OK then I get this error. **ERROR: (ENCSYT-16013): /sw/cadence/libraries/cmos065_522-2/CORL65LPSVT_5.1/CADENCE/LEF/ CORL65LPSVT_soc.lef failed I am...
    Posted to Digital Implementation (Forum) by Sohaib Qazi on Tue, Jan 10 2012
  • starting RTL compiler and Encounter

    Hi all I am totally new to encounter. I have written a VHDL code and intended to implement it using XFAB xh035 technology. I have read some tutorials online and the manual and found out that to use RC, I have to have a source script (.tcl file) and some library files. Where can I get the .tcl file and...
    Posted to Logic Design (Forum) by jun1119 on Thu, Nov 3 2011
Page 1 of 2 (14 items) 1 2 Next >