Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
3D-IC
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
More Products
OrCAD Products
Sigrity Technologies
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
Quicklinks
All Blogs
All Forums
Community Search
CDNLive User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> Jack Erickson
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
All Blog Categories
Popular Tags
Allegro
Analog
ARM
cadence
DAC
Digital Implementation
e
EDA360
encounter
ESL
functional verification
Incisive
industry insights
Low power
Mixed-Signal
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
TLM
UVM
Verification
Virtuoso
Browse All Tags
Email
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Share
Twitter
Facebook
LinkedIn
Google+
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
Jack Erickson
abstraction
Apple
ARM
CDNLive
CDNLive!
chip estimate
chip planning
chipestimate
clock gating
C-to-Silicon
C-to-Silicon 12.2
C-to-Silicon Compiler
DAC 2012
Design Explorer
Digital
EDA Graffiti
ESL
Flex Channels
Freescale
functional verification
High-Level Synthesis
hls
IBM
Imagination
innovation
IP
IP re-use
iPad
iPod
Israel
John Bruggeman
logic desgin
Logic Design
low power design
Madonna
MDV
metric-driven verification
MSMV
Multi-Supply Multi-Voltage
Physical Prediction
Physical Synthesis
Physical timing closure
ple physical global
QoR
RC-Physical
rock stars
RTL
RTL Compiler
RTL power estimation
software
spreadsheet
system design
System Design and Verification
System Design and Verifcation
SystemC
TLM
Twitter
UVM
video processor
Watanabe
webinar
C-to-Silicon 12.2 Available for Your Holiday Shopping List
The winter holiday season is that special time of year when we get bombarded with catalogs, emails, television commercials, banner ads, store displays, and any other method to get our attention on something that somebody is trying to sell. Having been trained as an engineer, I'm able to filter a...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Thu, Dec 13 2012
Speed Verification Turnaround by Extending Metric-Driven Verification (MDV) to TLM
One of the main benefits of moving the design entry point up in abstraction from RTL to SystemC/TLM is faster verification turnaround. Higher abstraction contains much fewer details, so simulation at that level runs faster and debug is much more productive. But in order to reduce overall verification...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Wed, Nov 28 2012
CDNLive paper: High-level Synthesis on Video Processing ASIC
The proceedings from the recent CDNLive! event in Israel recently became available, and you can access them with your Cadence.com account login. The paper entitled "High-level Synthesis on Video Processing ASIC" delivered by Yaniv Fais and Michael Zarubinsky of Freescale gives a great look...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Wed, Nov 14 2012
What Madonna Can Teach You About Chip Design
Rather than wandering too far off-track with this one, what celebrity is more well-known for successfully reinventing themselves than Madonna? And it's probably less about reinvention than it is about adapting to a changing marketplace. How many other 1980's pop stars can still sell out arenas...
Posted to
Logic Design
(Weblog)
by
Jack Erickson
on Fri, Mar 26 2010
What Can We Learn From The iPad About Chip Design?
You probably heard that Apple announced a touchscreen tablet computer last week. The announcement came with a lot of talk of it defining a new product category. That's somewhat laughable, since tablet computers have been around for a few years. BUT - the previous tablet computers were all based on...
Posted to
Logic Design
(Weblog)
by
Jack Erickson
on Tue, Feb 2 2010
Innovation != Invention
There's a common misperception, especially in technology fields, that invention and innovation are interchangeable terms. Innovation is a new solution to a problem, a new way of doing things, something that creates new markets and categories. Yes, an invention can enable innovation, but it is not...
Posted to
Logic Design
(Weblog)
by
Jack Erickson
on Tue, Nov 3 2009
How Much Power Are You Leaving On The Table?
Everybody is looking to reduce their chip's power consumption these days. Often a lot of reduction is needed in order to fit in the desired power envelope. Until now, designers of chips for wireless applications formed the majority of the power management community. These days, it is applicable to...
Posted to
Logic Design
(Weblog)
by
Jack Erickson
on Fri, Oct 23 2009
Physically-Aware Synthesis: This Time it’s Different
RTL Compiler Physical has been available for about 2 years now, and we're getting more customers all the time. But we still get the question - how is this different from physical synthesis tools like PKS or Physical Compiler? Those of you that were around 10 years ago when physical synthesis was...
Posted to
Logic Design
(Weblog)
by
Jack Erickson
on Fri, Oct 16 2009
SoC and remodeling cost estimation
Over at Cadence's Industry Insights blog by Richard Goering , he has a great writeup of a panel at the Virtual SoC Conference entitled "Are SoC Development Costs Significantly Underrated?" In it, there was a great analogy comparing a chip design project to a home remodeling project. This...
Posted to
Logic Design
(Weblog)
by
Jack Erickson
on Tue, Oct 6 2009
Branching Out - My Twitter Experiment
I enjoy writing on this blog, but I don't get to post nearly as much as I would like. So I am going to try posting more often over on Twitter. It should be less-formal and more conversational, which are both more up my alley. I will of course continue to post here, too. If you are interested, you...
Posted to
Logic Design
(Weblog)
by
Jack Erickson
on Mon, Oct 5 2009
Page 1 of 2 (12 items) 1
2
Next >