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DAC 2013 Panel – Can Better Organization Solve the Verification Crisis?
Automated tools and standardized methodologies have made functional verification easier, but verification is still arguably the biggest bottleneck in getting chips out the door. The good news, according to panelists at the recent Design Automation Conference ( DAC 2013 ), is that organizational and management...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jun 13 2013
System to Silicon Verification – CDNLive Gives a Reality Check on How Hardware and Software Meet
Ever since switching from being a hardware/software chip developer to being an enabler with tools in EDA and embedded software, I was part of a team working towards methodologies and tools to improve the interaction of hardware and software. In December last year -- 15 years in -- I summarized a great...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Fri, Mar 8 2013
Securing the Internet of Things
While I had looked at the challenges of hardware/software integration in various application domains like automotive , industrial and wireless before, I had the most unsettling experience last week at the Amphion Forum in San Francisco in the application area of device security. I am officially scared...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Wed, Dec 12 2012
User Presentation: Adapting a Specman “e” Simulation Testbench to Emulation
When Intel engineers were asked to verify one of the company's largest Many Integrated Core (MIC) designs, they faced a quandary. On one hand, they wanted the visibility and debug features provided by their Specman e language simulation environment. But they also wanted the much faster speeds provided...
Posted to
Industry Insights
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by
rgoering
on Thu, Aug 2 2012
FinFETs, Tri-Gate Transistors Promise Low Power – But Pose Some Design Challenges
At 14nm and below, it's a good bet that many IC designs will use a new 3D transistor technology called "FinFET" (or, to use Intel's term, "Tri-Gate"). With the promise of greatly reduced power at a given level of performance, there's much to like about FinFETs. But there...
Posted to
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rgoering
on Mon, Jul 23 2012
Video: Xuropa, Intel and Cadence Collaborate to Speed EDA in the Cloud
Cloud computing can generally support the types of workloads required by EDA tools, but when it comes to billion-gate semiconductor simulation, there's room for improvement. A recent collaboration between Xuropa, Intel and Cadence, presented at the user track at the June Design Automation Conference...
Posted to
Industry Insights
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rgoering
on Wed, Jun 27 2012
High-Level Synthesis Users: Productivity Gains Beckon, But Learning Curve Comes First
SystemC-based high-level synthesis (HLS) tools have greatly improved in recent years and are undergoing adoption by many large semiconductor companies. But to get high productivity out of HLS, current RTL designers will first face a learning curve, according to panelists at the recent Design Automation...
Posted to
Industry Insights
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rgoering
on Mon, Jun 25 2012
DAC 2012 Panelists Tackle Tough Questions About 2.5D-ICs and 3D-ICs
In a sometimes contentious panel session at the Design Automation Conference (DAC 2012) June 7, experts discussed and debated key technology and business questions around 2.5D-ICs and 3D-ICs. One overall takeaway is that 2.5D technology is very close to volume production, but true 3D stacking raises...
Posted to
Industry Insights
(Weblog)
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rgoering
on Thu, Jun 14 2012
DAC 2012: High-Level Synthesis Tutorial Standing Room Only
Monday is tutorial day at DAC, and this year the highest-attended tutorial was Synthesizing SystemC to Layout , led by Michael Bohm of Intel. The first session had over 100 attendees, standing room only: Later sessions each had over 50 attendees. The tutorial featured topics ranging from designing using...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Tue, Jun 5 2012
Gary Smith at DAC 2012: Multi-Platform Design and the $40M System on Chip
Veteran EDA analyst Gary Smith started his annual Design Automation Conference ( DAC 2012 ) presentation with three simple words: "I was wrong." Wrong, that is, about last year's observation that it takes $75 million or more to design the average high-end mobile semiconductor design. Smith...
Posted to
Industry Insights
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by
rgoering
on Sun, Jun 3 2012
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