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Intel,Industry Insights
14nm
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User Presentation: Adapting a Specman “e” Simulation Testbench to Emulation
When Intel engineers were asked to verify one of the company's largest Many Integrated Core (MIC) designs, they faced a quandary. On one hand, they wanted the visibility and debug features provided by their Specman e language simulation environment. But they also wanted the much faster speeds provided...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Aug 2 2012
FinFETs, Tri-Gate Transistors Promise Low Power – But Pose Some Design Challenges
At 14nm and below, it's a good bet that many IC designs will use a new 3D transistor technology called "FinFET" (or, to use Intel's term, "Tri-Gate"). With the promise of greatly reduced power at a given level of performance, there's much to like about FinFETs. But there...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jul 23 2012
Video: Xuropa, Intel and Cadence Collaborate to Speed EDA in the Cloud
Cloud computing can generally support the types of workloads required by EDA tools, but when it comes to billion-gate semiconductor simulation, there's room for improvement. A recent collaboration between Xuropa, Intel and Cadence, presented at the user track at the June Design Automation Conference...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jun 27 2012
High-Level Synthesis Users: Productivity Gains Beckon, But Learning Curve Comes First
SystemC-based high-level synthesis (HLS) tools have greatly improved in recent years and are undergoing adoption by many large semiconductor companies. But to get high productivity out of HLS, current RTL designers will first face a learning curve, according to panelists at the recent Design Automation...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jun 25 2012
DAC 2012 Panelists Tackle Tough Questions About 2.5D-ICs and 3D-ICs
In a sometimes contentious panel session at the Design Automation Conference (DAC 2012) June 7, experts discussed and debated key technology and business questions around 2.5D-ICs and 3D-ICs. One overall takeaway is that 2.5D technology is very close to volume production, but true 3D stacking raises...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jun 14 2012
Gary Smith at DAC 2012: Multi-Platform Design and the $40M System on Chip
Veteran EDA analyst Gary Smith started his annual Design Automation Conference ( DAC 2012 ) presentation with three simple words: "I was wrong." Wrong, that is, about last year's observation that it takes $75 million or more to design the average high-end mobile semiconductor design. Smith...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Jun 3 2012
Panelists Propose “Top Ten” Lists for Flash Memory Trends
What are the 10 most important things designers need to know about flash memory today? Participants in the closing panel of the Flash Memory Summit offered different lists, each coming from different perspectives, and each including insights and predictions that some may find to be surprising or controversial...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Aug 14 2011
DAC Panel Calls Off “Battle” Between Prototyping and Emulation
A Design Automation Conference (DAC) panel June 8 looked like it was destined for controversy. It was titled, "Software-Hardware Verification Battle: Prototyping vs. Emulation." But that battle didn't happen. Instead, most participants agreed that several types of hardware/software integration...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jun 14 2011
Gadi Singer DAC Keynote Cites “Imminent EDA Transformation”
Electronic design automation (EDA) will change rapidly and dramatically if Gadi Singer, vice president and general manager of Intel's SoC Enabling Group, has his way. In a keynote speech at the Design Automation Conference June 8 titled "The Imminent EDA Transformation," Singer called on...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jun 9 2011
EDP Workshop: Will Security Concerns Slow EDA in the Cloud?
Is public cloud computing secure enough for IC design work? Two different perspectives emerged at the IEEE Electronic Design Processes ( EDP ) workshop April 7-8, where an Intel manager detailed security concerns his company has about public clouds, and the CEO of EDA startup Physware explained why his...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Apr 13 2011
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