Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
3D-IC
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
More Products
OrCAD Products
Sigrity Technologies
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
The Fuller View Blog
Quicklinks
All Blogs
All Forums
Community Search
CDNLive User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> Intel/Cadence
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
The Fuller View Blog
All Blog Categories
Popular Tags
Allegro
ARM
cadence
DAC
Digital Implementation
e
EDA360
encounter
ESL
functional verification
Incisive
industry insights
IP
Low power
mixed-signal
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
TLM
UVM
verification
Virtuoso
Browse All Tags
Email
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Share
Twitter
Facebook
LinkedIn
Google+
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
Intel,Cadence
2.5D
2.5D-IC
3D
3D ecosystem
3D panel
3D-IC
Accelerated Verification IP
Acceleration
AMD
analysis
ARM
assembly
AVIP
billion gate
billion gate simulation
Bluespec
Borkar
C++
Calypto
CDNLive
CDNLive!
Clem Meas
cloud
cloud computing
cloud scheduling
CoWoS
C-to-Silicon Compiler
DAC
DAC 2011
DAC 2012
DAC 2013
DAC panel
DAC: DAC panel
DFM
DV engineers
dynamic power analysis
ECO
EDA
EDA in cloud
embedded software
emulation
emulator
ESL
extraction
Fast Models
FPGA
Freescael
Freescale
Functional Verification
Ganguly
hardware/software integration
High-level Synthesis
HLS
Hunter: ARM
IBM
Imperas
Incisive
Incorvaia
Industry Insights
Madden
Naresh Sehgal
NEC
OpenStack
packaging
Palladium
Palladium XP
Qualcomm
Simulation
Stanford
Stellfox
Synopsys
synthesis
System Design and Verification
System Development Suite
System to Silicon Verification
SystemC
system-level design
Teledyne LeCroy FPGA Based Prototyping
test
TLM
TSMC
TSV
VCP
verification
Verification Computing Platform
verification engineers
Verification IP
verification management
verification organization
video
virtual platforms
virtual prototypes
virtual prototyping
Virtual System Platform
Vivado
VSP
Xilinx
Xuropa
yield
zynq
DAC 2013 Panel – Can Better Organization Solve the Verification Crisis?
Automated tools and standardized methodologies have made functional verification easier, but verification is still arguably the biggest bottleneck in getting chips out the door. The good news, according to panelists at the recent Design Automation Conference ( DAC 2013 ), is that organizational and management...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jun 13 2013
System to Silicon Verification – CDNLive Gives a Reality Check on How Hardware and Software Meet
Ever since switching from being a hardware/software chip developer to being an enabler with tools in EDA and embedded software, I was part of a team working towards methodologies and tools to improve the interaction of hardware and software. In December last year -- 15 years in -- I summarized a great...
Posted to
System Design and Verification
(Weblog)
by
fschirrmeister
on Fri, Mar 8 2013
Video: Xuropa, Intel and Cadence Collaborate to Speed EDA in the Cloud
Cloud computing can generally support the types of workloads required by EDA tools, but when it comes to billion-gate semiconductor simulation, there's room for improvement. A recent collaboration between Xuropa, Intel and Cadence, presented at the user track at the June Design Automation Conference...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jun 27 2012
High-Level Synthesis Users: Productivity Gains Beckon, But Learning Curve Comes First
SystemC-based high-level synthesis (HLS) tools have greatly improved in recent years and are undergoing adoption by many large semiconductor companies. But to get high productivity out of HLS, current RTL designers will first face a learning curve, according to panelists at the recent Design Automation...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jun 25 2012
DAC 2012 Panelists Tackle Tough Questions About 2.5D-ICs and 3D-ICs
In a sometimes contentious panel session at the Design Automation Conference (DAC 2012) June 7, experts discussed and debated key technology and business questions around 2.5D-ICs and 3D-ICs. One overall takeaway is that 2.5D technology is very close to volume production, but true 3D stacking raises...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jun 14 2012
DAC Panel Calls Off “Battle” Between Prototyping and Emulation
A Design Automation Conference (DAC) panel June 8 looked like it was destined for controversy. It was titled, "Software-Hardware Verification Battle: Prototyping vs. Emulation." But that battle didn't happen. Instead, most participants agreed that several types of hardware/software integration...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jun 14 2011
Page 1 of 1 (6 items)