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Industry Insights,formal verification
72-hour
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DVCon 2013 Expert Panel: How to Succeed with Verification Planning
While formalized methodologies now exist for many aspects of functional verification, verification planning is still largely an ad-hoc process. Yet verification planning is becoming increasingly important as chips get more complex. At the recent DVCon 2013 conference, a panel of verification experts...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Mar 5 2013
DVCon 2013 Preview – Learn from Other Design and Verification Engineers
The Design and Verification Conference ( DVCon 2013 ) will be held Feb. 25-28 at the Doubletree Hotel in San Jose, California - and this year's program has something of interest for almost every design and verification engineer. The conference offers 12 technical sessions, 10 tutorials, two panels...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jan 24 2013
Webinar Report: Assertion-Based Verification IP Ensures ARM ACE Protocol Compliance
Do you want to enjoy the benefits of formal verification without having to become an expert? A newly archived Cadence webinar shows how you can do just that, using assertion-based verification IP (ABVIP) that supports both formal and dynamic verification of systems-on-chip using the ARM ACE protocol...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Dec 19 2012
Alberto Sangiovanni-Vincentelli at ICCAD: From Early EDA to the "Sensory Swarm"
Few people have been as influential in the development of EDA as Alberto Sangiovanni-Vincentelli , professor at the University of California at Berkeley and Cadence board member. At the International Conference on Computer-Aided Design (ICCAD ) Nov. 6, he delivered a presentation that ranged from the...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Nov 8 2012
Webinar Report: How Formal “Apps” Ease IC Verification
Formal verification applications, or "apps," can significantly lighten the IC verification workload without requiring a knowledge of assertion-based verification (ABV) - or even, in most cases, the need to write assertions. A recently archived Cadence webinar , held Aug. 8, 2012, describes...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Aug 16 2012
72-Hour Challenge Aims to “Prove” Formal Verification
Can formal verification technology take a large design, sight unseen, and produce meaningful results in 3 days? Cadence partner Oski Technology is betting the answer is "yes," and is offering to prove it at the Oski Live Formal Verification Challenge at the Design Automation Conference (DAC...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Mar 29 2012
Best Practices for Selecting and Using Verification IP (VIP)
In the past few years, commercial verification IP (VIP) has been selected for use in an ever greater percentage of verification environments. While VIP has the capability to save considerable time and engineering resources, there are several decisions you need to make in order to optimize the value received...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Feb 13 2012
Webinar Report: New Methodology Revs Up Code Coverage Analysis
Most IC verification teams use code coverage as signoff criteria, but they often have limited information about unreachable code. A new "case-splitting" methodology, described in a recently archived webinar, shows how a technique based on formal analysis provides new insight into coverage holes...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Feb 6 2012
Archived Webinar: Using Scoreboards With Formal Verification
If you've run simulation, you have probably used scoreboards to check that outputs properly match inputs. As revealed in a newly archived webinar, there's an easy way to use scoreboards with formal verification. It requires a slightly different methodology, but it turns out to be a good way to...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Dec 7 2011
“Assertion Synthesis” Webinar: Questions, Answers About NextOp BugScope
You know a webinar is hot when the questions just keep rolling on in from the audience and go well into overtime. Such was the case in a newly archived Cadence webinar titled "Automate Assertion Generation for Simulation, Formal and Emulation Flows." The webinar showed how "assertion synthesis...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Oct 17 2011
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